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All News of EDA Lab
2024-03 Keynote Speech at International Symposium on Physical Design (ISPD2024) title: Physical Design Challenges in Modern Heterogeneous Integration, ±iÄ£¤å (Yao-Wen Chang)
2024-03 ACM/IEEE Design Automation Conference (DAC2024) Paper title: Redistribution Layer Routing with Dynamic Via Insertion under Irregular Via Structure, ²ø­õºû (Je-Wei Chuang), §d©v¿« (Zong-Han Wu), ¶À¬f¿o (Bo-Ying Huang) and ±iÄ£¤å (Yao-Wen Chang)
2024-03 ACM/IEEE Design Automation Conference (DAC2024) Paper title: Mixed-Size 3D Analytical Placement with Heterogeneous Technology Nodes, ³¯«Û¿² (Yan-Jen Chen), ÁÂ©Ó­× (Cheng-Hsiu Hsieh), Ĭ¬f¿« (Po-Han Su), ³¯¤Öµ¾ (Shao-Hsiang Chen) and ±iÄ£¤å (Yao-Wen Chang)
2023-12 ®¥³ßÂÅ·Ó²N¦P¾Ç¡B§f¤¸µ¾¦P¾Ç¡BĬ¸h²N¦P¾ÇºaÀò¡u2023 CAD Contest °ê¤ºÁÉCÃDÀuµ¥¡v
2023-12 ®¥³ß½²©v¿o¦P¾Ç¡B³¯¶{ÂE¦P¾Ç¡B¦¿¬ý½å¦P¾Ç¡B§õ©Ó«Û¦P¾ÇºaÀò¡u2023 CAD Contest °ê¤ºÁÉDÃD¯SÀu¡v
2023-11 1st Place at the 2023 CAD Contest Problem B at ICCAD, ³¯«Û¿² (Yan-Jen Chen), ÁÂ©Ó­× (Cheng-Hsiu Hsieh), ³¯¤Öµ¾ (Shao-Hsiang Chen), Ĭ¬f¿« (Po-Han Su)
2023-11 2nd Place at the 2023 21th ACM CADathlon Contest at ICCAD, ³¯«Û¿² (Yan-Jen Chen) and ÁÂ©Ó­× (Cheng-Hsiu Hsieh)
2023-11 International Symposium on Physical Design (ISPD2024) Paper title: Satisfiability Modulo Theories-Based Qubit Mapping for Trapped-Ion Quantum Computing Systems, ´¿Þmµ¾ (Wei-Hsiang Tseng), ±iÄ£¤å (Yao-Wen Chang), and ¦¿¤¶§» (Jie-Hong Roland Jiang)
2023-10 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2023) Paper title: A General Wavelength-Routed Optical Networks-on-Chip Model with Applications to Customized and Fault-Tolerant Topology Designs, ³¯«ÛÀM (Yan-Lin Chen), ´¿Þm­õ (Wei-Che Tseng), °ª°¶³ó (Wei-Yao Kao), and ±iÄ£¤å (Yao-Wen Chang)
2023-10 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2023) Paper title: Floorplanning for the Embedded Multi-die Interconnect Bridge (EMIB) Package, §õ±R¹Å (Chung-Chia Lee) and ±iÄ£¤å (Yao-Wen Chang)
2023-04 ACM/IEEE Design Automation Conference (DAC2023) Paper title: Late Breaking Results: An Efficient Bridge-based Compression Algorithm for Topologically Quantum Error Corrected Circuits, ´¿Þmµ¾ (Wei-Hsiang Tseng) and ±iÄ£¤å (Yao-Wen Chang)
2023-04 ACM/IEEE Design Automation Conference (DAC2023) Paper title: Late Breaking Results: Analytical Placement for 3D ICs with Multiple Manufacturing Technologies, ³¯«Û¿² (Yan-Jen Chen), ³¯¨¥Þ± (Yan-Syuan Chen), ´¿Þm­õ (Wei-Che Tseng), «¸©Ó¦ö (Cheng-Yu Chiang), ù¬Rµ¾ (Yu-Hsiang Lo), and ±iÄ£¤å (Yao-Wen Chang)
2023-02 ACM/IEEE Design Automation Conference (DAC2023) Paper title: PUFFER: A Routability-Driven Placement Framework via Cell Padding with Multiple Features and Strategy Exploration, Zhijie Cai, Peng Zou, Zhengtao Wu, Xingyu Tong, «\­x (Jun Yu), ³¯«Ø§Q (Jianli Chen), and ±iÄ£¤å (Yao-Wen Chang)
2023-02 ACM/IEEE Design Automation Conference (DAC2023) Paper title: A Matching Based Escape Routing Algorithm with Variable Design Rules and Constraints, Qinghai Liu, Disi Lin, Chuandong Chen, Huan He, ³¯«Ø§Q (Jianli Chen), and ±iÄ£¤å (Yao-Wen Chang)
2023-02 ACM/IEEE Design Automation Conference (DAC2023) Paper title: Disjoint-Path and Golden-Pin Based Irregular PCB Routing with Complex Constraints, Qinghai Liu, Qinfei Tang, Jiarui Chen, Chuandong Chen, ¦¶¦ÛµM (Ziran Zhu), Huan He, ³¯«Ø§Q (Jianli Chen), and ±iÄ£¤å (Yao-Wen Chang)
2023-02 ACM/IEEE Design Automation Conference (DAC2023) Paper title: Toward Parallelism-Optimal Topology Generation for Wavelength-Routed Optical NoC Designs, ³¯«a¸Û (Kuan-Cheng Chen), ³¯«ÛÀM (Yan-Lin Chen), §f¯§ª@ (Yu-Sheng Lu) and ±iÄ£¤å (Yao-Wen Chang)
2023-02 ACM/IEEE Design Automation Conference (DAC2023) Paper title: Graph-Based Simultaneous Placement and Routing for Two-Dimensional Directed Self-Assembly Technology, ³¯«Â¦° (Wei-Hsu Chen) and ±iÄ£¤å (Yao-Wen Chang)
2023-02 ACM/IEEE Design Automation Conference (DAC2023) Paper title: Any-Angle Routing for Redistribution Layers in 2.5D IC Packages, ÁéÌÉ°a (Min-Hsuan Chung), ²ø­õºû (Je-Wei Chuang), and ±iÄ£¤å (Yao-Wen Chang)
2022-09 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2022) Paper title: SGIRR: sparse graph index remapping for ReRAM crossbar operation unit and power optimization, ¤ý¬F¤¸ (Cheng-Yuan Wang), ±iÄ£¤å (Yao-Wen Chang), and Yuan-Hao Chang
2022-09 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2022) Paper title: Obstacle-Avoiding Multiple Redistribution Layer Routing with Irregular Structures, ³¯«Û§Ê (Yen-Ting Chen), and ±iÄ£¤å (Yao-Wen Chang)
2022-09 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2022) Paper title: Transitive closure graph-based warpage-aware floorplanning for package designs, ®}·z (Yang Hsu), ÁéÌÉ°a (Min-Hsuan Chung), ±iÄ£¤å (Yao-Wen Chang), and Ci-Hong Lin
2022-07 ®¥³ß§f¯§ª@ºaÀò²Ä¤Q¤E©¡»OÆW¿nÅé¹q¸ô³]­p¾Ç·| (TICD) ³Õ¤h½×¤å¼ú
2022-04 2nd Place at 2022 ACM ISPD Security Closure of Physical Layouts Contest, ³\­PÞ³, ³¯«a¸Û, ù¬Rµ¾, ³¯¨¥Þ±, and ±iÄ£¤å (Yao-Wen Chang)
2022-03 ACM/IEEE Design Automation Conference (DAC2022) Paper title: High-performance Placement for Large-scale Heterogeneous FPGAs with Clock Constraints, ¦¶¦ÛµM (Ziran Zhu), Yangjie Mei, Zijun Li, Jingwen Lin, ³¯«Ø§Q (Jianli Chen), Jun Yang, and ±iÄ£¤å (Yao-Wen Chang)
2022-03 ACM/IEEE Design Automation Conference (DAC2022) Paper title: CNN-inspired Analytical Global Placement for Large-scale Heterogeneous FPGAs, Huimin Wang, Xingyu Tong, Chenyue Ma, Runming Shi, ³¯«Ø§Q (Jianli Chen), Kun Wang, «\­x (Jun Yu), and ±iÄ£¤å (Yao-Wen Chang)
2022-03 ACM/IEEE Design Automation Conference (DAC2022) Paper title: Y-architecture-based Flip-Chip Routing with Dynamic Programming-based Bend Minimization, ¿ÔT¦p (Szu-Ru Nie), ³¯«Û§Ê (Yen-Ting Chen), and ±iÄ£¤å (Yao-Wen Chang)
2022-03 ACM/IEEE Design Automation Conference (DAC2022) Paper title: Thermal-aware Optical-electrical Routing Codesign for On-Chip Signal Communications, §f¯§ª@ (Yu-Sheng Lu), ³¯«a¸Û (Kuan-Cheng Chen), Yu-Ling Hsu, and ±iÄ£¤å (Yao-Wen Chang)
2022-03 ACM/IEEE Design Automation Conference (DAC2022) Paper title: A Bridge-based Algorithm for Simultaneous Primal and Dual Defects Compression on Topologically Quantum-error-corrected Circuits, ´¿Þmµ¾ (Wei-Hsiang Tseng), and ±iÄ£¤å (Yao-Wen Chang)
2022-01 IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC-2022) Paper title: High-Correlation 3D Routability Estimation for Congestion-guided Global Routing, Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, ³¯«Ø§Q (Jianli Chen), and ±iÄ£¤å (Yao-Wen Chang)
2022-01 IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC-2022) Paper title: Voronoi Diagram Based Heterogeneous Circuit Layout Centerline Extraction for Mask Verification, Xiqiong Bai, ¦¶¦ÛµM (Ziran Zhu), Peng Zou, ³¯«Ø§Q (Jianli Chen), «\­x (Jun Yu), and ±iÄ£¤å (Yao-Wen Chang)
2021-12 ®¥³ßĬ½Y¬v¦P¾Ç¡B§dºÕ°a¦P¾Ç¡B½²¨K¬§¦P¾Ç¡BªL¤©±d¦P¾ÇºaÀò¡u2021 CAD Contest °ê¤ºÁÉBÃD¯SÀu¡v
2021-12 ±iÄ£¤å±Ð±ÂºaÀò¡u±Ð¨|³¡¾Ç³N¼ú¡v
2021-11 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2021) Paper title: On-chip Optical Routing with Waveguide Matching Constraints, ²øÃL¦t (Fu-Yu Chuang) and ±iÄ£¤å (Yao-Wen Chang)
2021-11 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2021) Paper title: A Row-Based Algorithm for Non-Integer Multiple-Cell-Height Placement, ªL¤l³ó (Zih-Yao Lin) and ±iÄ£¤å (Yao-Wen Chang)
2021-11 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2021) Paper title: Time-Division Multiplexing Based System-Level FPGA Routing, ¼Bºû³Í (Wei-Kai Liu), ³¯©ú§» (Ming-Hung Chen), ±i®a»Ê (Chia-Ming Chang), ±i®¶¹Å (Chen-Chia Chang), and ±iÄ£¤å (Yao-Wen Chang)
2021-08 ®¥³ß§f¯§ª@¦P¾Ç¡B³¯«a¸Û¦P¾Ç¡B³\¯§ºð¦P¾ÇºaÀò¡u2021 VLSI Design/CAD Symposium ¤j·|³Ì¨Î½×¤å¼ú¡v
2021-03 ACM/IEEE Design Automation Conference (DAC2021) Paper title: Simultaneous Pre-and Free-assignment Routing for Multiple Redistribution Layers with Irregular Vias, ½²¦t³Ç (Yu-Jie Cai), ®}·z (Yang Hsu), and ±iÄ£¤å (Yao-Wen Chang)
2021-03 ACM/IEEE Design Automation Conference (DAC2021) Paper title:VLSI Structure-aware Placement for Convolutional Neural Network Accelerator Units, ©P©û (Yun Chou), ³\­PÞ³ (Jhih-Wei Hsu), ±iÄ£¤å (Yao-Wen Chang), and ³¯ªF³Ç (Tung-Chieh Chen)
2021-03 ACM/IEEE Design Automation Conference (DAC2021) Paper title: A Bridge-based Compression Algorithm for Topological Quantum Circuits, ®}±áµq (Chen-Hao Hsu), ªL©{¸© (Wan-Hsuan Lin), ´¿Þmµ¾ (Wei-Hsiang Tseng), and ±iÄ£¤å (Yao-Wen Chang)
2021-03 ACM/IEEE Design Automation Conference (DAC2021) Paper title: Performance-driven simultaneous partitioning and routing for multi-FPGA systems, ³¯©ú§» (Ming-Hung Chen), ±iÄ£¤å (Yao-Wen Chang), and ¤ý«T³Ç (Jun-Jie Wang)
2021-03 ACM/IEEE Design Automation Conference (DAC2021) Paper title: Two-Stage Neural Network Classifier for the Data Imbalance Problem with Application to Hotspot Detection, Bingshu Wang, Lanfan Jiang, ¦¶¤å¿³ (Wenxing Zhu), ³¢Às©[ (Longkun Guo), ³¯«Ø§Q (Jianli Chen), and ±iÄ£¤å (Yao-Wen Chang)
2020-12 ±iÄ£¤å±Ð±ÂºaÁt¡u2020 ACM Fellow¡v
2020-09 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2020) Paper title: Routability-Aware Pin Access Optimization for Monolithic 3D Designs, ¤ý¼í¤@ (Run-Yi Wang) and ±iÄ£¤å (Yao-Wen Chang)
2020-02 ACM/IEEE Design Automation Conference (DAC2020) Paper title: Via-Based Redistribution Layer Routing for InFO Packages with Irregular Pad Structures, 温²»§Ê (Hsiang-Ting Wen), ½²¦t³Ç (Yu-Jie Cai), ®}·z (Yang Hsu) and ±iÄ£¤å (Yao-Wen Chang)
2020-02 ACM/IEEE Design Automation Conference (DAC2020) Paper title: Topological Structure and Physical Layout Codesign for Wavelength-Routed Optical Networks-on-Chip, §f¯§ª@ (Yu-Sheng Lu), ´åª@¿Ä (Sheng-Jung Yu), and ±iÄ£¤å (Yao-Wen Chang)
2020-02 ACM/IEEE Design Automation Conference (DAC2020) Paper title: A Provably Good Wavelength-Division-Multiplexing-Aware Clustering Algorithm for On-Chip Optical Routing, §f¯§ª@ (Yu-Sheng Lu), ´åª@¿Ä (Sheng-Jung Yu), and ±iÄ£¤å (Yao-Wen Chang)
2020-02 ACM/IEEE Design Automation Conference (DAC2020) Paper title: Latch Clustering for Timing-Power Co-Optimization, ¶À´Âµ^ (Chau-Chin Huang), Gustavo Tellez, Gi-Joon Nam, and ±iÄ£¤å (Yao-Wen Chang)
2020-02 ACM/IEEE Design Automation Conference (DAC2020) Paper title: Hamiltonian Path Based Mixed-Cell-Height Legalization for Neighbor Diffusion Effect Mitigation, ³¯«Ø§Q (Jianli Chen), ¦¶¦ÛµM (Ziran Zhu), Qinghai Liu, Yimin Zhang, ¦¶¤å¿³ (Wenxing Zhu), and ±iÄ£¤å (Yao-Wen Chang)
2020-02 ACM/IEEE Design Automation Conference (DAC2020) Paper title: Time-Division Multiplexing Based System-Level FPGA Routing for Logic Verification, Peng Zou, Zhifeng Lin, Xiao Shi, Yingjie Wu, ³¯«Ø§Q (Jianli Chen), «\­x (Jun Yu), and ±iÄ£¤å (Yao-Wen Chang)
2020-02 ACM/IEEE Design Automation Conference (DAC2020) Paper title: An Efficient EPIST Algorithm for Global Placement with Non-Integer Multiple-Height Cells, ³¯«Ø§Q (Jianli Chen), Zhipeng Huang, Ye Huang, ¦¶¤å¿³ (Wenxing Zhu), «\­x (Jun Yu) and ±iÄ£¤å (Yao-Wen Chang)
2019-09 IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC-2019) Paper title: Unified Redistribution Layer Routing for 2.5D IC Packages, ½±§g²[ (Chun-Han Chiang), ²øÃL¦t (Fu-Yu Chuang), and ±iÄ£¤å(Yao-Wen Chang)
2019-08 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2019) Paper title: Obstacle-Aware Group-Based Length-Matching Routing for Pre-Assignment Area-I/O Flip-Chip Designs, ±i¨|Þ± (Yu-Hsuan Chang), 温²»§Ê (Hsiang-Ting Wen), and ±iÄ£¤å (Yao-Wen Chang)
2019-08 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2019) Paper title: Graph- and ILP-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly, ¤ý¥e²Þ (Zhan-Ling Wang), and ±iÄ£¤å (Yao-Wen Chang)
2019-08 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2019) Paper title: Timing-Aware Fill Insertions with Design-Rule and Density Constraints, Äõ®x²` (Tingshen Lan), §õ¿³Åv (Xingquan Li), ³¯«Ø§Q (Jianli Chen), «\­x (Jun Yu), ¦ó½U (Lei He), ¸³´ËµØ (Senhua Dong), ¦¶¤å¿³ (Wenxing Zhu), and ±iÄ£¤å (Yao-Wen Chang)
2019-08 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2019) Paper title: Analytical Placement with 3D Poisson's Equation and ADMM based Optimization for Large-Scale 2.5D Heterogeneous FPGAs, ³¯«Ø§Q (Jianli Chen), ¦¶¤å¿³ (Wenxing Zhu), «\­x (Jun Yu), ¦ó½U (Lei He), and ±iÄ£¤å (Yao-Wen Chang)
2019-06 ACM/IEEE Design Automation Conference (DAC2019) Paper title: A DAG-Based Algorithm for Obstacle-Aware Topology-Matching On-Track Bus Routing, ®}±áµq (Chen-Hao Hsu), ¬x²Ð¶v (Shao-Chun Hung), ³¯©þ (Hao Chen), ®]¤Z¯Ñ (Fan-Keng Sun), and ±iÄ£¤å (Yao-Wen Chang)
2019-06 ACM/IEEE Design Automation Conference (DAC2019) Paper title: BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit Placement, ®]¤Z¯Ñ (Fan-Keng Sun) and ±iÄ£¤å (Yao-Wen Chang)
2019-04 2nd Place at 2019 ACM ISPD Initial Detailed Routing Contest, ±i®¶¹Å (Chen-Chia Chang), ±i®a»Ê (Chia-Ming Chang), ¼Bºû³Í (Wei-Kai Liu), ®}±áµq (Chen-Hao Hsu), and ±iÄ£¤å (Yao-Wen Chang)
2018-11 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2018) Paper title: A Multithreaded Initial Detailed Routing Algorithm Considering Global Routing Guides, ®]¤Z¯Ñ (Fan-Keng Sun), ³¯©þ (Hao Chen), ³¯´º¥Ñ (Ching-Yu Chen), ®}±áµq (Chen-Hao Hsu), and ±iÄ£¤å (Yao-Wen Chang)
2018-11 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2018) Paper title: Mixed-Cell-Height Placement with Complex Minimum-Implant-Area Constraints, ³¯«Ø§Q (Jianli Chen), Peng Yang, §õ¿³Åv (Xingquan Li), ¦¶¤å¿³ (Wenxing Zhu), and ±iÄ£¤å (Yao-Wen Chang)
2018-11 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2018) Paper title: Mixed-Cell-Height Legalization Considering Technology and Region Constraints, ¦¶¦ÛµM (Ziran Zhu), §õ¿³Åv (Xingquan Li), Yuhang Chen, ³¯«Ø§Q (Jianli Chen), and ±iÄ£¤å (Yao-Wen Chang)
2018-11 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2018) Paper title: Mixed-Cell-Height Placement Considering Drain-To-Drain Abutment, ´¿¨|¬° (Yu-Wei Tseng) and ±iÄ£¤å (Yao-Wen Chang)
2018-11 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2018) Paper title: Simultaneous Partitioning and Signals Grouping for Time-Division Multiplexing in 2.5D FPGA-Based Systems, ³¯¤h¶v (Shih-Chun Chen), Richard Sun, and ±iÄ£¤å (Yao-Wen Chang)
2018-11 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2018) Paper title: Novel Proximal Group ADMM for Placement Considering Fogging and Proximity Effects, ³¯«Ø§Q (Jianli Chen), §õ¶§ (Li Yang), ´^¬@ (Zheng Peng), ¦¶¤å¿³ (Wenxing Zhu), and ±iÄ£¤å (Yao-Wen Chang)
2018-11 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2018) Paper title: Analytical Solution of Poisson's Equation and Its Application to VLSI Global Placement, ¦¶¤å¿³ (Wenxing Zhu), ¶À§ÓÄP (Zhipeng Huang), ³¯«Ø§Q (Jianli Chen), and ±iÄ£¤å (Yao-Wen Chang)
2018-08 ºÖ¦{¤j¾Ç³¯«Ø§Q±Ð±ÂÀò±o¤¤°ê­pºâ¾÷¾Ç·|(CCF)¶°¦¨¹q¸ôEarly Career Award
2018-08 ½±§g²[¡B²øÃL¦tÀò±o²Ä¤G¤Q¤E©¡VLSI Design/CAD Symposium¤j·|³Ì¨Î½×¤å¼ú
2018-07 »O¤j¸ê¤u¨tªL©¾½n±Ð±ÂÀò±o±Ð¨|³¡¥É¤s«C¦~¾ÇªÌ­pµe¸É§U
2018-07 »O¬ì¤j¹q¾÷¨t¤èÊo¤ª±Ð±ÂÀò±o¬ì§Þ³¡·R¦]´µ©Z­pµe¸É§U
2018-04 3rd Place at 2018 ACM ISPD Initial Detailed Routing Contest, ³¯©þ (Hao Chen), ®}±áµq (Chen-Hao Hsu), ®]¤Z¯Ñ (Fan-Keng Sun), ³¯´º¥Ñ (Ching-Yu Chen), and ±iÄ£¤å (Yao-Wen Chang)
2018-04 3rd Place at 2018 ACM ISPD Initial Detailed Routing Contest, ³¯©þ (Hao Chen), ®}±áµq (Chen-Hao Hsu), ®]¤Z¯Ñ (Fan-Keng Sun), ³¯´º¥Ñ (Ching-Yu Chen), and ±iÄ£¤å (Yao-Wen Chang)
2018-03 ACM/IEEE Design Automation Conference (DAC2018) Paper title: Generalized Augmented Lagrangian and Its Applications to VLSI Global Placement, ¦¶¦ÛµM(Ziran Zhu), ³¯«Ø§Q(Jianli Cheni), ´^¬@(Zheng Peng), ¦¶¤å¿³(Wenxing Zhu), and ±iÄ£¤å (Yao-Wen Chang)
2018-03 ACM/IEEE Design Automation Conference (DAC2018) Paper title: Efficient Multi-Layer Obstacle-Avoiding Region-to-Region Rectilinear Steiner Tree Construction, ¤ý¼í¤@(Run-Yi Wang), ¥Õ®a¸Û(Chia-Cheng Pai), ¤ý«T³Ç(Jun-Jie Wang), 温²»§Ê(Hsiang-Ting Wen), ¥Õ¯§©Ó(Yu-Cheng Pai), ±iÄ£¤å (Yao-Wen Chang), §õ«Ø¼Ò(James CM Li), and ¦¿¤¶§»(Jie-Hong Jiang)
2018-03 ACM/IEEE Design Automation Conference (DAC2018) Paper title: WB-Trees: A Topological Representation for FinFET-Based Analog Layout Designs, §f¯§ª@(Yu-Sheng Lu), ±i¨|Þ±(Yu-Hsuan Chang), and ±iÄ£¤å (Yao-Wen Chang)
2017-12 106¾Ç¦~«×±Ð¨|³¡¥D¿ì¤j¾Ç®Õ°|¿nÅé¹q¸ô¹q¸£»²§U³]­p³nÅé»s§@ÄvÁÉ ©wÃD²Õ¨Î§@: ¤ý¼í¤@¡B¤ý«T³Ç¡B·Å²»§Ê¡B³¯¬fÀM
2017-11 ±iÄ£¤å±Ð±ÂÀò¿ï¬°IEEE Council on EDA(CEDA) 2018-2019¦~«×­Ô¥ô·|ªø©M2020-2021¦~«×·|ªø
2017-10 §d«Û»öÀò±o¤¤°ê¹q¾÷¤uµ{¾Ç·|106¦~«C¦~½×¤å¼ú²Ä¤@¦W (±iÄ£¤å±Ð±Â«ü¾É)
2017-09 ±iÄ£¤å±Ð±ÂºaÀò²Ä24©¡ªF¤¸¼ú (¹q¾÷/¸ê°T/³q°T¬ì§Þ»â°ì)
2017-07 »O¬ì¤j¹q¾÷¨t¤èÊo¤ª±Ð±ÂºaÀò²Ä¤K©¡TICD³Ç¥X¦~»´¾ÇªÌ¼ú
2017-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2017) Paper title: Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints, §d«Û»ö (Yen-Yi Wu) and ±iÄ£¤å (Yao-Wen Chang)
2017-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2017) Paper title: Clock-Aware Placement for Large-Scale Heterogeneous FPGAs, ³¢úÞ½è (Yun-Chih Kuo), ¶À´Âµ^ (Chau-Chin Huang), ³¯¤h¶v (Shih-Chun Chen), ½±§g²[ (Chun-Han Chiang), ±iÄ£¤å (Yao-Wen Chang), and ³¢´µ«Û (Sy-Yen Kuo)
2017-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2017) Paper title: Redistribution Layer Routing for Wafer-Level Integrated Fan-Out Package-on-Packages, ªL®x¦{ (Ting-Chou Lin), ãu®a§Ó (Chia-Chih Chi) and ±iÄ£¤å (Yao-Wen Chang)
2017-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2017) Paper title: An Integrated-Spreading-Based Macro-Refining Algorithm for Large-Scale Mixed-Size Circuit Designs, ³¯«äÅM (Szu-To Chen), ±iÄ£¤å (Yao-Wen Chang) and ³¯ªF³Ç (Tung-Chieh Chen)
2017-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2017) Paper title: A Novel Damped-Wave Framework for Macro Placement, ±i®Ê»¨ (Chin-Hao Chang), ±iÄ£¤å (Yao-Wen Chang) and ³¯ªF³Ç (Tung-Chieh Chen)
2017-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2017) Paper title: Blockage-Aware Terminal Propagation for Placement Wirelength Minimization, ·¨³Ó¬° (Sheng-Wei Yang), ±iÄ£¤å (Yao-Wen Chang) and ³¯ªF³Ç (Tung-Chieh Chen)
2017-06 ¶À´Âµ^Àò±o2016¦~«×Ápµo¬ì§Þ³Ð·s¬ãµo¤¤¤ß³Õ¤h¯Z¤H¤~°ö¨|¼ú¾Çª÷
2017-05 Ĭ¨|¸©Àò±o2016¦~«×»OÆW¿nÅé¹q¸ô³]­p¾Ç·|³Õ¤h½×¤å¼ú
2017-05 §d¤@ÄPÀò±o2016¦~«×»OÆW¿nÅé¹q¸ô³]­p¾Ç·|ºÓ¤h½×¤å¼ú
2017-04 2nd Place at 2017 ACM ISPD FPGA Placement Contest, ³¢úÞ½è (Yun-Chih Kuo), ¶À´Âµ^ (Chau-Chin Huang), ³¯¤h¶v (Shih-Chun Chen), ½±§g²[ (Chun-Han Chiang), ±iÄ£¤å (Yao-Wen Chang), and ³¢´µ«Û (Sy-Yen Kuo)
2017-02 ACM/IEEE Design Automation Conference (DAC2017) Paper title: Fogging Effect Aware Placement in Electron Beam Lithography, ¶À¤_¯u (Yu-Chen Huang), ±iÄ£¤å (Yao-Wen Chang)
2017-02 ACM/IEEE Design Automation Conference (DAC2017) Paper title: Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs, ³¯«Ø§Q (Jianli Chen), ¦¶¦ÛµM (Ziran Zhu), ¦¶¤å¿³ (Wenxing Zhu), and ±iÄ£¤å (Yao-Wen Chang) (Best Paper Nominee)
2017-02 ACM/IEEE Design Automation Conference (DAC2017) Paper title: Graph-Based Logic Bit Slicing for Datapath-Aware Placement, ¶À´Âµ^ (Chau-Chin Huang), ªL¬f¹´ (Bo-Qiao Lin), §õ©ý¿o (Hsin-Yin Lee), ±iÄ£¤å (Yao-Wen Chang), §d°ê³Ó (Kuo-Sheng Wu), and ·¨§g´¼ (Jun-Zhi Yang)
2017-02 ACM/IEEE Design Automation Conference (DAC2017) Paper title: Detailed Placement for Two-Dimensional Directed Self-Assembly Technology, ªL´Ó¤å(Zhi-Wen Lin), ±iÄ£¤å (Yao-Wen Chang)
2017-01 104¾Ç¦~«×±Ð¨|³¡¥D¿ì¤j¾Ç®Õ°|¿nÅé¹q¸ô¹q¸£»²§U³]­p³nÅé»s§@ÄvÁÉ ©wÃD²Õ¨Î§@: §d«Û»ö ©wÃD²Õ¨Î§@: ªL®x¦{¡B¤ý¥e²Þ¡B§E®ü®S
2017-01 Ĭ¨|¸©Àò±o¥xÆW¤j¾Ç¹q¤l©Ò104¾Ç¦~«×³Ì¨Î³Õ¤h½×¤å¼ú
2017-01 §d¤@ÄPÀò±o¥xÆW¤j¾Ç¹q¤l©Ò104¾Ç¦~«×³Ì¨ÎºÓ¤h½×¤å¼ú
2016-12 ¶À´Âµ^¡B§d¤@ÄPÀò±o¥xÆW¤j¾Ç¹q¤l©Ò2016¦~¡u¾Ç¥Í³Ç¥X¬ã¨s¼ú¡v
2016-10 §d¤@ÄPÀò±o¤¤°ê¹q¾÷¤uµ{¾Ç·|105¦~«C¦~½×¤å¼ú²Ä¤@¦W (±iÄ£¤å±Ð±Â«ü¾É)
2016-08 Best Paper Award of EDA Session in the 27th VLSI Design/CAD Symposium, Taiwan. Paper title: An effective RDL routing algorithm for the InFO WLCSP technology, ªL¬f¹´, ªL®x¦{, ±iÄ£¤å
2016-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2016) Paper title: Redistribution layer routing for integrated fan-out wafer-level chip-scale packages, ªL¬f¹´ (Bo-Qiao Lin), ªL®x¦{ (Ting-Chou Lin) and ±iÄ£¤å (Yao-Wen Chang)
2016-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2016) Paper title: VCR: simultaneous via-template and cut-template-aware routing for directed self-Assembly technology, Ĭ¨|¸© (Yu-Hsuan Su) and ±iÄ£¤å (Yao-Wen Chang)
2016-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2016) Paper title: DSA-compliant routing for two-dimensional patterns using block copolymer lithography, Ĭ¨|¸© (Yu-Hsuan Su) and ±iÄ£¤å (Yao-Wen Chang)
2016-04 International Symposium on Physical Design (ISPD2016) Paper title: Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs, ªL´Ó¤å (Zhi-Wen Lin), ±iÄ£¤å (Yao-Wen Chang)
2016-02 ACM/IEEE Design Automation Conference (DAC2016) Paper title: Timing-Driven Cell Placement Optimization for Early Slack Histogram Compression, ¶À´Âµ^ (Chau-Chin Huang), ¼B«Û§g (Yen-Chun Liu), §f¦öª@ (Yu-Sheng Lu), ³¢úÞ½è (Yun-Chih Kuo), and ±iÄ£¤å (Yao-Wen Chang)
2016-02 ACM/IEEE Design Automation Conference (DAC2016) Paper title: QB-Trees: Towards An Optimal Topological Representation with Applications to Analog Layout Designs, §d¤@ÄP (I-Peng Wu), ¼ÚÓT»x (Hung-Chih Ou), and ±iÄ£¤å (Yao-Wen Chang)
2016-02 ACM/IEEE Design Automation Conference (DAC2016) Paper title: Minimum-Implant-Area-Aware Detailed Placement with Spacing Constraints, ´¿·¢²[ (Kai-Han Tseng) and ±iÄ£¤å (Yao-Wen Chang)
2015-12 ±iÄ£¤å±Ð±ÂÀò¿ï¾á¥ô¡u2016-2017 IEEE CEDA ·|ij°ÆÁ`µô¡v
2015-11 ±iÄ£¤å±Ð±ÂºaÀò IEEE Council on EDA (CEDA) Outstanding Service Award
2015-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2015) Paper title: Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region Constraints, ¶À´Âµ^ (Chau-Chin Huang), §õ©ý¿o (Hsin-Ying Lee), ªL¬f¾ô (Bo-Qiao Lin), ·¨³Ó¬° (Sheng-Wei Yang), ±i®Ê»¨ (Chin-Hao Chang), ³¯«äÅM (Szu-To Chen), and ±iÄ£¤å (Yao-Wen Chang)
2015-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2015) Paper title: Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask Fabrication, ªL´Ó¤å (Zhi-Wen Lin), ¤èÊo¤ª (Shao-Yun Fang), ±iÄ£¤å (Yao-Wen Chang), ÄÇ°¶¥¿ (Wei-Cheng Rao) and ºÞ³Ç¶¯ (Chieh-Hsiung Kuan )
2015-04 1st Place at 2015 ACM ISPD Blockage-Aware Detailed Routing-Driven Placement Contest, ¶À´Âµ^ (Chau-chin Huang), ·¨³Ó¬° (Sheng-Wei Yang), ±i®Ê»¨ (Chin-Hao Chang), §õ©ý¿o (Hsin-Ying Lee), ³¯«äÅM (Szu-To Chen), ªL¬f¹´ (Bo-Qiao Lin), and ±iÄ£¤å (Yao-Wen Chang)
2015-02 ACM/IEEE Design Automation Conference (DAC2015) Paper title: Cutting Structure-Aware Analog Placement Based on Self-Aligned Double Patterning with E-Beam Lithography, ¼ÚÓT»x (Hung-Chih Ou), ´¿·¢²[ (Kai-Han Tseng), and ±iÄ£¤å (Yao-Wen Chang)
2015-02 ACM/IEEE Design Automation Conference (DAC2015) Paper title: Layout-Dependent-Effects-Aware Analytical Analog Placement, ¼ÚÓT»x (Hung-Chih Ou), ´¿·¢²[ (Kai-Han Tseng), ¼B¬L«Û (Jhao-Yan Liu), §d¤@ÄP (I-Peng Wu), and ±iÄ£¤å (Yao-Wen Chang)
2015-02 ACM/IEEE Design Automation Conference (DAC2015) Paper title: Nanowire-aware Routing Considering High Cut Mask Complexity, Ĭ¨|¸©(Yu-Hsuan Su) and ±iÄ£¤å (Yao-Wen Chang)
2015-02 ACM/IEEE Design Automation Conference (DAC2015) Paper title: Routing-Architecture-Aware Analytical Placement for Heterogeneous FPGAs, ³¯¸t«Û(Sheng-Yen Chen), and ±iÄ£¤å(Yao-Wen Chang)
2014-09 IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC-2014) Paper title: Detailed-Routing-Driven Analytical Standard-Cell Placement, ¶À´Âµ^ (Chau-Chin Huang), ªô«Ø¶¯ (Chien-Hsiung Chiou), ´¿·¢²[ (Kai-Han Tseng), and ±iÄ£¤å(Yao-Wen Chang)
2014-09 IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC-2014) Paper title: Layout Decomposition for Spacer-is-Metal (SIM) Self-Aligned Double Patterning, ¤èÊo¤ª (Shao-Yun Fang ), À¹Öö®Ñ(Yi-Shu Tai), ±iÄ£¤å(Yao-Wen Chang)
2014-09 IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC-2014) Paper title: Non-Stitch Triple Patterning-Aware Routing Based on Conflict Graph Pre-Coloring, ³\³Õ¶®(Po-Ya Hsu), ±iÄ£¤å(Yao-Wen Chang)
2014-07 IEEE International Conference on Computer Design (ICCD2014) Paper title : Simultaneous EUV flare- and CMP-Aware Placement, ¯d±Ò­ì (Chi-Yuan Liu), and ±iÄ£¤å (Yao-Wen Chang)
2014-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2014) Paper title:Efficient and Effective Packing and Analytical Placement for Large-Scale Heterogeneous FPGAs, ³¯¬R¿²(Yu-Chen Chen), ³¯¸t«Û(Sheng-Yen Chen), and ±iÄ£¤å(Yao-Wen Chang)
2014-06 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2014) Paper title: Fast Lithographic Mask Optimization Considering Process Variation, Ĭ¨|¸©(Yu-Hsuan Su), ¶À¤_¯u(Yu-Chen Huang), ½²«G¸s(Liang-Chun Tsai), ±iÄ£¤å(Yao-Wen Chang), Shayak Banerjee
2014-02 ACM/IEEE Design Automation Conference (DAC2014) Paper title: Overlay-aware Detailed Routing for Self-Aligned Double Patterning Lithography Using the Cut Process, ¼B¤S¤¯ (Iou-Jen Liu), ¤èÊo¤ª (Shao-Yun Fang), and ±iÄ£¤å (Yao-Wen Chang
2014-02 ACM/IEEE Design Automation Conference (DAC2014) Paper title: A New Asynchronous Pipeline Template for Power and Performance Optimization, ¦ó«a½å (Kuan-Hsien Ho), ±iÄ£¤å (Yao-Wen Chang)
2014-02 ACM/IEEE Design Automation Conference (DAC2014) Paper title: Functional ECO Using Metal-Configurable Gate-Array Spare Cells, ±iµØ¦t(Hua-Yu Chang), ¦¿¿·¦p(Iris Hui-Ru Jiang), and ±iÄ£¤å(Yao-Wen Chang)
2014-02 ACM/IEEE Design Automation Conference (DAC2014) Paper title: Routability-Driven Blockage-Aware Macro Placement, ³¯«³¤è (Yi-Fang Chen), ¶À´Âµ^ (Chau-Chin Huang), ªô«Ø¶¯ (Chien-Hsiung Chiou), and ±iÄ£¤å (Yao-Wen Chang)
2014-02 ACM/IEEE Design Automation Conference (DAC2014) Paper title: Simultaneous EUV Flare Variation Minimization and CMP Control with Coupling-Aware Dummification, ¯d±Ò­ì (Chi-Yuan Liu), «¸¼z¦p (Hui-Ju Jiang), and ±iÄ£¤å (Yao-Wen Chang)
2014-02 ±iÄ£¤å±Ð±ÂºaÀò°ê¬ì·|102¦~«×³Ç¥X¬ã¨s¼ú
2014-01 ±iÄ£¤å±Ð±ÂÀò¿ï¾á¥ô¡u2014-2015 IEEE CEDA §Þ³N¬¡°Ê°ÆÁ`µô¡v
2013-12 ³¯¸t«ÛºaÀòÁpµú¬ì§Þ¼ú¾Çª÷
2013-11 1st Place at the 2013 ACM/IEEE CAD Contest at ICCAD (Legalization and Detailed Placement Contest), ¶À´Âµ^ (Chau-Chin Huang), ªô«Ø¶¯ (Chien-Hsiung Chiou) ªL´Ó¤å( Zhi-Wen Lin), ´¿·¢²[ (Kai-Han Tseng), and ±iÄ£¤å(Yao-Wen Chang)
2013-11 3rd Place at the 2013 ACM/IEEE CAD Contest at ICCAD (Mask Optimization Contest), Ĭ¨|¸© (Yu-Hsuan Su), ¶À¤_¯u (Yu-Chen Huang) , ½²«G¸s (Liang-Chun Tsai), and ±iÄ£¤å (Yao-Wen Chang)
2013-08 ¼ÚÓT»xºaÀòÁpµo¬ì§Þ¼ú¾Çª÷ (MediaTek Fellowship)
2013-06 ±iÄ£¤å±Ð±ÂºaÀò DAC Prolific Author in a Single Year at the 50th DAC
2013-06 ±iÄ£¤å±Ð±ÂºaÀò DAC First Most Papers in Fifth Decade at the 50th DAC
2013-06 ±iÄ£¤å±Ð±ÂºaÀò DAC Long (12+ years) Publication Streak at the 50th DAC
2013-06 ±iÄ£¤å±Ð±ÂºaÀò DAC Prolific Author Award at the 50th DAC
2013-02 ACM/IEEE Design Automation Conference (DAC2013) Paper title: Stitch-Aware Routing Framework for Multiple E-Beam Lithography, ¤èÊo¤ª (Shao-Yun Fang), ¼B¤S¤¯ (Iou-Jen Liu), and ±iÄ£¤å (Yao-Wen Chang)
2013-02 ACM/IEEE Design Automation Conference (DAC2013) Paper title: Double Patterning Lithography-Aware Analog Placement, ±i²©¯ªK (Hsing-Chih Chang-Chien), ¼ÚÓT»x (Hung-Chih Ou), ³¯ªF³Ç (Tung-Chieh Chen), Ta-Yu Kuan, and ±iÄ£¤å (Yao-Wen Chang)
2013-02 ACM/IEEE Design Automation Conference (DAC2013) Paper title: Coupling-Aware Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits, ¼ÚÓT»x (Hung-Chih Ou), ¦ó«a½å (Kuan-Hsien Ho), ±iÄ£¤å (Yao-Wen Chang), and ±ä¿·ªÚ (Hui-Fang Tsao)
2013-02 ACM/IEEE Design Automation Conference (DAC2013) Paper title: An Efficient and Effective Analytical Placer for FPGAs, ªL¤l«í (Tzu-Hen Lin), Pritha Banerjee, and ±iÄ£¤å (Yao-Wen Chang)
2013-02 ACM/IEEE Design Automation Conference (DAC2013) Paper title: Multiple Chip Planning for Chip-Interposer Codesign, ¦ó¤¸³Í (Yuan-Kai Ho), and ±iÄ£¤å (Yao-Wen Chang)
2013-02 ACM/IEEE Design Automation Conference (DAC2013) Paper title: Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations, ¼ÚÓT»x (Hung-Chih Ou), ±i²©¯ªK (Hsing-Chih Chang-Chien), and ±iÄ£¤å (Yao-Wen Chang)
2013-02 ACM/IEEE Design Automation Conference (DAC2013) Paper title: Routability-Driven Placement for Hierarchical Mixed-Size Circuit Designs, ®}©s·¢ (Meng-Kai Hsu), ³¯«³¤è (Yi-Fang Chen), ¶À´Âµ^ (Chau-Chin Huang), and ±iÄ£¤å (Yao-Wen Chang)
2012-11 ±iÄ£¤å±Ð±ÂºaÀò 2013 IEEE Fellow
2012-11 ©Pª@ºaÀò¤¤°ê¹q¾÷¤uµ{¾Ç·|101¦~«C¦~½×¤å¼ú (±iÄ£¤å±Ð±Â«ü¾É)
2012-11 3rd Place at the 2012 CAD Contest at ICCAD, ³¯«³¤è (Yi-Fang Chen) and ¶À´Âµ^ (Chau-Chin Huang)
2012-11 3rd Place at the 2012 CAD Contest at ICCAD, ¯d±Ò­ì (Chi-Yuan Liu), ³¯¸t«Û (Sheng-Yen Chen) and ¼B¤S¤¯ (Iou-Jen Liu)
2012-11 1st Place at the 2012 SIGDA's CADathlon at ICCAD, ¼ÚÓT»x (Hung-Chih Ou) and ³\³Õ¶® (Po-Ya Hsu)
2012-09 ¤èÊo¤ªºaÀò¥x¿n¹q³Ç¥X¾Ç¥Í¬ã¨s¼ú»È¼ú
2012-06 1st Place at the 2012 ACM/SIGDA Student Research Competition (Graduate Student Category), ¤èÊo¤ª (Shao-Yun Fang )
2012-06 1st Place at the DAC 2012 Routability-Driven Placement Contest, ®}©s·¢ (Meng-Kai Hsu) and ±iÄ£¤å (Yao-Wen Chang)
2012-04 1st Place of 2012 ACM ISPD Discrete Gate Sizing Contest, ¦ó«a½å (Kuan-Hsien Ho) , ³\³Õ¶® (Po-Ya Hsu), ³¯¬R¿² (Yu-Chen Chen), and ±iÄ£¤å (Yao-Wen Chang)
2012-02 ACM/IEEE Design Automation Conference (DAC2012) Paper title: Obstacle-Avoiding Free-assignment Routing for Flip-Chip Designs, §õ¬f½n(Po-Wei Lee), §õºü¾e(Hsu-Chieh Lee), ¦ó¤¸³Í(Yuan-Kai Ho), ±iÄ£¤å(Yao-Wen Chang), ªL¨Ì¼ä(I-Jye Lin), and Cindy Shen
2012-02 ACM/IEEE Design Automation Conference (DAC2012) Paper title: Non-uniform Multilevel Analog Routing with Matching Constraints, ¼ÚÓT»x(Hung-Chih Ou), ±i²©¯ªK (Hsing-Chih Chang-Chien), and ±iÄ£¤å(Yao-Wen Chang)
2012-02 ACM/IEEE Design Automation Conference (DAC2012) Paper title: Simultaneous Flare Level and Flare Variation Minimization with Dummification in EUVL, ¤èÊo¤ª(Shao-Yun Fang) and ±iÄ£¤å(Yao-Wen Chang)
2012-02 ACM/IEEE Design Automation Conference (DAC2012) Paper title: A Novel Layout Decomposition Algorithm for Triple Patterning Lithography, ¤èÊo¤ª(Shao-Yun Fang), ³¯«Â¦t(Wei-Yu Chen), and ±iÄ£¤å(Yao-Wen Chang)
2012-02 ACM/IEEE Design Automation Conference (DAC2012) Paper title: Structure-Aware Placement for Datapath Intensive Circuit Designs, ©Pª@(Sheng Chou), ®}©s·¢(Meng-Kai Hsu), and ±iÄ£¤å(Yao-Wen Chang)
2012-02 ACM/IEEE Design Automation Conference (DAC2012) Paper title: A Chip-Package-Board Co-Design Methodology, §õºü¾e(Hsu-Chieh Lee) and ±iÄ£¤å(Yao-Wen Chang)
2012-02 ACM/IEEE Design Automation Conference (DAC2012) Paper title: Timing ECO Optimization Using Metal-Configurable Gate-Array Spare Cells, ±iµØ¦t(Hua-Yu Chang), ¦¿¿·¦p(Hui-Ru Jiang), and ±iÄ£¤å(Yao-Wen Chang)
2011-10 §õºü¾eºaÀò¤¤°ê¹q¾÷¤uµ{¾Ç·|100¦~«C¦~½×¤å¼ú (±iÄ£¤å±Ð±Â«ü¾É)
2011-09 EDA ¹êÅç«Ç¦b³»¦y´Á¥ZIEEE TCAD ³sÄò¥|¦~(2007-2010)½×¤åµoªí¼Æ¨C¦~¥@¬É²Ä¤@
2011-09 EDA ¹êÅç«Ç³sÄò¤»¦~ (2006-2011) ¦b³»¦y°ê»Ú·|ijIEEE/ACM ICCAD½×¤åµoªí¼Æ¨C¦~¥@¬É²Ä¤@
2011-09 EDA ¹êÅç«Ç³sÄò¤»¦~ (2006-2011) ¦b³»¦y°ê»Ú·|ijIEEE/ACM ICCAD©M ACM/IEEE DAC½×¤åµoªíÁ`¼Æ¨C¦~¥@¬É²Ä¤@
2011-09 ¼ÚÓT»xºaÀò¥x¿n¹q¼ú¾Çª÷ (TSMC scholarship)
2011-09 1st Winner of 2011 IEEE CEDA PATMOS-TAC Contest, ¦ó«a½å (Kuan-Hsien Ho) , ¦ó¤¸³Í (Yuan-Kai Ho), and ±iÄ£¤å (Yao-Wen Chang)
2011-08 ¬I«HÞ³ºaÀòÁpµo¬ì§Þ¼ú¾Çª÷ (MediaTek Fellowship)
2011-08 §õºü¾eºaÀò±ÀÂ˦¨¬°¤¤µØ¥Á°ê´´³³´´ºaÅA¾Ç·|100¦~ºaÅA·|­û
2011-08 ©P¨¹«ÛºaÀò±ÀÂ˦¨¬°¤¤µØ¥Á°ê´´³³´´ºaÅA¾Ç·|100¦~ºaÅA·|­û
2011-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2011) Paper title: Escape Routing for Staggered-Pin-Array PCBs, ¦ó¤¸³Í(Yuan-Kai Ho), §õºü¾e(Hsu-Chieh Lee), and ±iÄ£¤å(Yao-Wen Chang)
2011-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2011) Paper title: Power Reduction by Placement and Clock-Network Co-Synthesis for Pulsed-Latch Designs, ²ø©öÀM(Yi-Lin Chuang), ªL­i§Ê(Hong-Ting Lin), ¦ó©v©ö(Tsung-Yi Ho), ±iÄ£¤å(Yao-Wen Chang), and Diana Marculescu
2011-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2011) Paper title: Routability-Driven Analytical Placement for Mixed-Size Circuit Designs, ®}©s·¢(Meng-Kai Hsu), ©Pª@(Sheng Chou), ªL¤l«í(Tzu-Hen Lin), and ±iÄ£¤å(Yao-Wen Chang)
2011-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2011) Paper title: Timing ECO Optimization via Criticality Identification and Bezier Curve Smoothing, ±iµØ¦t(Hua-Yu Chang), ¦¿¿·¦p(Iris Hui-Ru Jiang), and ±iÄ£¤å(Yao-Wen Chang)
2011-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2011) Paper title: A Corner Stitching Compliant B*-tree Representation and Its Applications to Analog Placement, ±ä¿·ªÚ(Hui-Fang Tsao), ©P¨¹«Û(Pang-Yen Chou), ¶À¤h­Û(Shih-Lun Huang), ±iÄ£¤å(Yao-Wen Chang), ªL¬f§»(Po-Hung Lin), Duan-Ping Chen, and Dick Liu
2011-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2011) Paper title: Heterogeneous B*-trees for Analog Placement with Symmetry and Regularity Considerations, ©P¨¹«Û(Pang-Yen Chou), ¼ÚÓT»x(Hung-Chih Ou), and ±iÄ£¤å(Yao-Wen Chang)
2011-05 ±iÄ£¤å±Ð±ÂºaÀò¹q¸ê¾Ç°|100¦~«×¾Ç³N°^Äm¼ú
2011-02 ACM/IEEE Design Automation Conference (DAC2011) Paper title: TSV-Aware Analytical Placement for 3D IC Designs, ®}©s·¢(Meng-Kai Hsu), ±iÄ£¤å(Yao-Wen Chang), and Valeriy Balabanov (Best Paper Nominee)
2011-02 ACM/IEEE Design Automation Conference (DAC2011) Paper title: Simultaneous functional and timing ECO, ±iµØ¦t(Hua-Yu Chang), ¦¿¿·¦p(Hui-Ru Jiang), and ±iÄ£¤å(Yao-Wen Chang)
2011-02 ±iÄ£¤å±Ð±ÂºaÀò99¦~«×°ê¬ì·|³Ç¥X¬ã¨s¼ú
2010-11 The #1 worldwide in the citation ranking in the category of Hardware & Architecture in the Microsoft Academic Search Database link
2010-10 §õ¬f½nÀò±o¤¤°ê¹q¾÷¤uµ{¾Ç·|«C¦~½×¤å¼ú²Ä¤@¦W
2010-10 Best Paper Award in IEEE International Conference on Computer Design (ICCD2010) Paper title: Provably good OPC modeling and its applications to interconnect optimization, ¶À¤h­Û(S.-L. Huang), ªL©¾½n(C.-W. Lin), and ±iÄ£¤å(Y.-W. Chang)
2010-09 ±iÄ£¤å±Ð±ÂºaÀò 2010 IBM Faculty Award
2010-09 ³\´Ü¶¯¡B±iÄ£¤åºaÀò 99¦~«×»O¤j¬ìªL½×¤å¼úÀuµ¥¼ú
2010-08 ±iÄ£¤å±Ð±Âºa¤É¥xÆW¤j¾Ç¹q¤l¤uµ{¾Ç¬ã¨s©Ò©Òªø
2010-08 Best Paper Award of EDA Session in the 21th VLSI Design/CAD Symposium, Taiwan. Paper title: ECO Timing and Mask-Cost Optimization with Redundant Wires, ¤èÊo¤ª, ²¦õ¦|, ±iÄ£¤å
2010-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: Design-Hierarchy Aware Mixed-Size Placement for Routability Optimization, ²ø©öÀM(Yi-Lin Chuang), Gi-Joon Nam, Charles J. Alpert, ±iÄ£¤å(Yao-Wen Chang), Jarrod Roy, and Natarajan Viswanathan
2010-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: Native-Conflict-Aware Wire Perturbation for Double Patterning Technology, ³¯«ä¦ö(Szu-Yu Chen) and ±iÄ£¤å(Yao-Wen Chang) (Best Paper Nominee)
2010-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: High Variation-Tolerant Obstacle-Avoiding Clock Mesh Synthesis with Symmetrical Driving Trees, ¬I«HÞ³(Xin-Wei Shih), §õºü¾e(Hsu-Chieh Lee), ¦ó«a½å(Kuan-Hsien Ho), and ±iÄ£¤å(Yao-Wen Chang)
2010-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: Template-Mask Design Methodology for Double Patterning Technology, ³\´Ü¶¯(Chin-Hsiung Hsu), ±iÄ£¤å(Yao-Wen Chang), and Sani R. Nassif
2010-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs, ®}©s·¢(Meng-Kai Hsu) and ±iÄ£¤å(Yao-Wen Chang)
2010-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: Redundant-Wires-Aware ECO Timing and Mask-Cost Optimization, ¤èÊo¤ª(Shao-Yun Fang), ²¦õ¦|(Tzuo-Fan Chien), and ±iÄ£¤å(Yao-Wen Chang)
2010-06 ¤E¤Q¤K¾Ç¦~«×±Ð¨|³¡¥D¿ì¤j¾Ç®Õ°|¿nÅé¹q¸ô¹q¸£»²§U³]­p³nÅé»s§@ÄvÁÉ ©wÃD²Õ¨Î§@: ¼B«T§»
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2010-03 NTUclock Àò 2010 ACM/IEEE ISPD °ê»Ú¹q¤l³]­p¦Û°Ê¤Æ³nÅé¬ãµoÄvÁɲĤT¦W; ¬ãµo¹Î¶¤: ¬I«HÞ³, §õºü¾e, ¦ó«a½å, ±iÄ£¤å
2010-02 ACM/IEEE Design Automation Conference (DAC2010) Paper title: Fast Timing-Model Independent Buffered Clock-Tree Synthesis, ¬I«HÞ³(Xin-Wei Shih) and ±iÄ£¤å(Yao-Wen Chang)
2010-02 ACM/IEEE Design Automation Conference (DAC2010) Paper title: Pulsed-latch-aware placement for timing-integrity optimization, ²ø©öÀM(Yi-Lin Chuang), Sangmin Kim, Youngsoo Shin, and ±iÄ£¤å(Yao-Wen Chang)
2010-02 ACM/IEEE Design Automation Conference (DAC2010) Paper title: Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips, ªLÑg¦t(Cliff Chiung-Yu Lin) and ±iÄ£¤å(Yao-Wen Chang)
2009-12 ¤è®a°¶Àò±o¥xÆW¤j¾Ç¹q¤l©Ò97¾Ç¦~«×³Ì¨Î³Õ¤h½×¤å¼ú
2009-10 ªLÑg¦tºaÀò¡u¤¤°ê¹q¾÷¤uµ{¾Ç·|98¦~«C¦~½×¤å¼ú¡v²Ä¤@¦W
2009-10 ¹êÅç«Ç¦b³»¦y´Á¥ZIEEE TCAD 2008½×¤åµoªí¼Æ¥@¬É²Ä¤@
2009-10 ¹êÅç«Ç³sÄò¤T¦~ (2007-2009) ¦b³»¦y°ê»Ú·|ijACM/IEEE DAC¤ÎIEEE/ACM ICCAD½×¤åµoªí¼Æ¥@¬É²Ä¤@
2009-09 IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC-2010) Paper title: TRECO: Dynamic Technology Remapping for Timing Engineering Change Orders, Kuan-Hsien Ho, Jie-Hong Roland Jiang, Yao-Wen Chang
2009-09 IEEE/ACM Asia South Pacific Design Automation Conference (ASP-DAC-2010) Paper title: Blockage-Avoiding Buffered Clock-Tree Synthesis for Clock Latency-Range and Skew Minimization, Xin-Wei Shih, Chung-Chun Cheng, Yuan-Kai Ho and Yao-Wen Chang
2009-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009) Paper title: BIST Design Optimization for Large-Scale Embedded Memory Cores, Tzuo-Fan Chien, Wen-Chi Chao, Chien-Mo Li, Kuan-Yu Liao, Ming-Tung Chang, Min-Hsiu Tsai, and Chih-Mou Tseng
2009-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009) Paper title: Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs, Yi-Lin Chuang, Po-Wei Lee, and Yao-Wen Chang
2009-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009) Paper title: Simultaneous Layout Migration and Decomposition for Double Patterning Technology, Chin-Hsiung Hsu, Yao-Wen Chang, Sani R. Nassif
2009-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009) Paper title: An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs, Po-Wei Lee, Chung-Wei Lin, Yao-Wen Chang
2009-06 ¤E¤Q¤C¾Ç¦~«×±Ð¨|³¡¥D¿ì¤j¾Ç®Õ°|¿nÅé¹q¸ô¹q¸£»²§U³]­p³nÅé»s§@ÄvÁÉ
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2009-04 NTUclock Àò 2009 ACM/IEEE ISPD °ê»Ú¹q¤l³]­p¦Û°Ê¤Æ³nÅé¬ãµoÄvÁɲĤ@¦W; ¬ãµo¹Î¶¤: ¬I«HÞ³, ¦ó¤¸³Í, ¾G¥ò¶v, ±iÄ£¤å
2009-04 ACM/IEEE Design Automation Conference (DAC2009) Paper title: Flip-Chip Routing with Unified Area-I/O Pad Assignments for Package-Board Co-Design, ¤è®a°¶(Jia-Wei Fang), Martin D. F. Wong, ±iÄ£¤å(Yao-Wen Chang)
2009-04 ACM/IEEE Design Automation Conference (DAC2009) Paper title: Thermal-driven analog placement considering device matching, ªL¬f§»(P.-H. Lin), ±i§»³Õ(H. Zhang), Martin D. F. Wong, ±iÄ£¤å(Yao-Wen Chang)
2009-04 ACM/IEEE Design Automation Conference (DAC2009) Paper title: Spare-Cell-Aware Multilevel Analytical Placement, ¦¿­õºû, ®}©s·¢, »¯¶}¤¸, ±iÄ£¤å(Yao-Wen Chang)
2009-04 ACM/IEEE Design Automation Conference (DAC2009) Paper title: ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochip, ªLÑg¦t(Cliff Chiung-Yu Lin), ±iÄ£¤å(Yao-Wen Chang)
2009-02 ¦ó¤¸³Í¡B¬I«HÞ³Àò±o¡u97¾Ç¦~«×¥xÆW¿nÅé¹q¸ô»s³yªÑ¥÷¦³­­¤½¥qÃÙ§U¥x¤j¹q¤l©ÒEDA²Õ³Õ¤h¯Z¬ã¨s¥Í¼ú¾Çª÷¡v
2009-01 ³¯ªF³ÇÀò±o¥xÆW¤j¾Ç¹q¤l©Ò96¾Ç¦~«×³Ì¨Î³Õ¤h½×¤å¼ú
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2008-12 ³¯ªF³Ç¡B¦¿­õºû¡B³¯¬Ó¦t¡B³\´Ü¶¯Àò±o2008¦~¥xÆW¤j¾Ç³Ç¥Xªí²{¼ú¾Çª÷
2008-09 ²ø©öÀM¡B¦ó«a½åÀò±o2008¦~¹q¤l©Ò¬ì§Þ­^»y²³ø¤ñÁɲĤT¦W
2008-09 ®}©s·¢Àò±o·s«ä¬ì§Þ2008³Õ¤h¯Z¼ú¾Çª÷
2008-09 ³¯«ä¦ö (²Ä¤G¦W)¤J³ò2008¦~²Ä¤C©¡°ê»Ú ACM CADathlon at ICCAD ÄvÁÉ¥xÆW°ö°V¨M¿ï
2008-09 ±iÄ£¤å±Ð±ÂÀò±o¥xÆW¤j¾Ç¡u±Ð¾ÇÀu¨}¼ú¡v(Excellent Teacher Award)
2008-08 ®}©s·¢ ¹q¤l©ÒEDA²Õ³Õ¤h¯Zª½¤É²Ä¤@¦W
2008-08 ³¯¬Ó¦t¡B©P«äºÍ¡B±iÄ£¤åºaÀòVLSI Design/CAD Symposium, 2008 CAD²Õ³Ì¨Î½×¤å¼ú
2008-07 ³¯®õ㸺aÀò¨H¤å¤¯±Ð±Â¦~«×½×¤å¼ú
2008-07 ³¯®õ㸡B¹ù¥ú¸U¡B¦¿­õºû¡BªL¬f§»¡B¦ó¤¸³Í¡B³¯ªF³Ç¡B³ëªÃÂE¡B±iÄ£¤åÀò±o«ä·½¬ì§Þ±Ð¨|°òª÷·|2008¦~EDA¼úÀyª÷ (DAC2008)
2008-07 ³¯«H¦¨¡B²ø©öÀM¡B¤è®a°¶¡B¦ó«a½å¡B³\´Ü¶¯¡B³¯¬Ó¦t¡B±iÄ£¤åÀò±o«ä·½¬ì§Þ±Ð¨|°òª÷·|2008¦~EDA¼úÀyª÷ (ICCAD2008)
2008-07 ®}©s·¢, ¹q¤l©ÒEDA²ÕºÓ¤h¯Z¦¨ÁZ²Ä¤G¦W
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2008-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2008) Paper title: Routing for Chip-Package-Board Co-Design Considering Differential Pairs, ¤è®a°¶(Jia-Wei Fang), ¦ó«a½å(Kuan-Hsien Ho), ±iÄ£¤å(Yao-Wen Chang)
2008-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2008) Paper title: Area-I/O Flip-Chip Routing for Chip-Package Co-Design, ¤è®a°¶(Jia-Wei Fang), ±iÄ£¤å(Yao-Wen Chang)
2008-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008) Paper title: "Multi-layer global routing considering via and wire capacities" ³\´Ü¶¯(C.-H. Hsu), ³¯¬Ó¦t(H.-Y. Chen), ±iÄ£¤å(Y.-W. Chang)
2008-07 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2008) Paper title: Constraint Graph-Based Macro Placement for Mixed-Size Circuit Designs, ³¯«H¦¨(Hsin-Chen Chen), ²ø©öÀM(Yi-Lin Chuang), ±iÄ£¤å(Yao-Wen Chang), ±i¥Ã©¾(Yung-Chung Chang)
2008-04 ACM/IEEE Design Automation Conference (DAC2008) Paper title: Analog Placement Based on Hierarchical Module Clustering, ªL¬f§»(Po-Hung Lin), Shyh-Chang Lin
2008-04 ACM/IEEE Design Automation Conference (DAC2008) Paper title: An Integrated Nonlinear Placement Framework with Congestion and Porosity Aware Buffer Planning, ³¯ªF³Ç(Tung-Chieh Chen), Ashutosh Chakraborty, David Z. Pan
2008-04 ACM/IEEE Design Automation Conference (DAC2008) Paper title: Predictive Formulae for OPC with Applications to Lithography-Friendly Routing, ³¯®õã¸, ¹ù¥ú¸U, ±iÄ£¤å(Best Paper Award nominee)
2008-04 ACM/IEEE Design Automation Conference (DAC2008) Paper title: Routability-Driven Analytical Placement by Net Overlapping Removal for Large-Scale Mixed-Size Designs, ¦¿­õºû, Ĭ¬f¿o, ±iÄ£¤å
2008-04 ACM/IEEE Design Automation Conference (DAC2008) Paper title: A Progressive-ILP Based Routing Algorithm for Cross-Referencing Biochips, ³ëªÃÂE, S. S. Sapatnekar, ·¨¨Î¬Â, ±iÄ£¤å
2008-04 NTUgr Àò 2008 ACM/IEEE ISPD °ê»Ú¹q¤l³]­p¦Û°Ê¤Æ³nÅé¬ãµoÄvÁɲĤG¦W; ¬ãµo¹Î¶¤: ³¯¬Ó¦t, ³\´Ü¶¯, ±iÄ£¤å
2007-12 ³\³ÍµaÀò±o2007¦~¡u¼ï¤å²W¤å±Ð°òª÷·|¼ú¾Çª÷¡v
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2007-11 ªLÑg¦t, 2007¦~¥x¤j¹q¤l©ÒEDA²ÕºÓ¤hºÂ¸Õ¤J¾Ç²Ä¤@¦W
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2007-11 ¥»¹êÅç«Ç µoªí³»¦y·|ij IEEE/ACM ICCAD ½×¤å 6½g, ¥þ¥@¬É²Ä¤@¦W
2007-11 ±iÄ£¤å±Ð±ÂÀòÁܾá¥ô³»¦y´Á¥Z IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ½s¿è
2007-11 ±iÄ£¤å±Ð±ÂÀòÁܾá¥ô³»¦y·|ij 2008 IEEE/ACM ICCAD °õ¦æ©e­û (Executive Committee)
2007-11 ±iÄ£¤å±Ð±Â¦A¦¸ÀòÁܾá¥ô³»¦y·|ij 2008 ACM/IEEE DAC ijµ{©e­û (Technical Program Committee)
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2007-09 ³¯«ä¦ö (²Ä¤@¦W)¡B³¯¬Ó¦t (²Ä¤­¦W )¡B³\´Ü¶¯(²Ä¤­¦W)¤J³ò 2007¦~²Ä¤»©¡°ê»Ú ACM CADathlon at ICCAD ÄvÁÉ¥xÆW°ö°V¨M¿ï
2007-09 ³ëªÃÂEÀò±oProf. Margarida Jacome Memorial Travel Award for ICCAD
2007-09 ³\´Ü¶¯Àò±o¡u¥xÆW·s«ä¬ì§ÞªÑ¥÷¦³­­¤½¥qEDA²Õ³Õ¤h¯Z¬ã¨s¥Í¼ú¾Çª÷¡v
2007-09 ªL©¾½n¡B±iÄ£¤åºaÀò¬ìªL½×¤å¼ú(Lam Thesis Award)Àuµ¥¼ú
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2007-08 Best Paper Award of EDA in the 18th VLSI Design/CAD Symposium, Taiwan. Paper title: A Network-Flow Based Algorithm for Digital Microfluidic Biochip Routing, ³ëªÃÂE, ·¨¨Î¬Â, ±iÄ£¤å
2007-06 ¤E¤Q¤­¾Ç¦~«×±Ð¨|³¡¥D¿ì¤j¾Ç®Õ°|¿nÅé¹q¸ô¹q¸£»²§U³]­p³nÅé»s§@ÄvÁÉ©wÃD²Õ¯SÀu: ³\³Íµa¡B¶À¤h­Û¡B§õ©s²»¡BªL©¾½n
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2007-04 ACM/IEEE Design Automation Conference (DAC2007) Paper title: MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs, ³¯ªF³Ç, ³ëªÃÂE, ±iÄ£¤å, ¶ÀºÖ§U(MTK), ¼B¨å©¨(MTK)
2007-04 ACM/IEEE Design Automation Conference (DAC2007) Paper title: A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages, ¼B§»¼Ý, §õ°ûµÓ, ±iÄ£¤å
2007-04 ACM/IEEE Design Automation Conference (DAC2007) Paper title: Analog Placement based on Novel Symmetry-Island Formulation, ªL¬f§», ªL¥@©÷(Springsoft)
2007-04 ACM/IEEE Design Automation Conference (DAC2007) Paper title: An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design, ¤è®a°¶, ³´Ü¶¯, ±iÄ£¤å (best paper nominee; received the highest score in the beyond-die track)
2007-04 »¯¤åºö, ¹q¤l©Ò EDA ²ÕºÓ¤h¯Z¦Ò¸Õ²Ä¤@¦W
2007-04 ²¦õ¦|, ¹q¾÷©Ò CS ²ÕºÓ¤h¯Z¦Ò¸Õ²Ä¤@¦W
2006-12 ¦¿­õºû, ³¯«H¦¨Àò±o¥xÆW¤j¾Ç³Ç¥Xªí²{¼ú
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2006-11 ³¯ªF³Ç, ¦¿­õºûÀò±oICCAD CADathlon²Ä¤T¦W(3rd place)
2006-10 ³\´Ü¶¯Àò±o¡u¥xÆW¿nÅé¹q¸ô»s³yªÑ¥÷¦³­­¤½¥qEDA²Õ³Õ¤h¯Z¬ã¨s¥Í¼ú¾Çª÷¡v
2006-09 ©P«äºÍ, ¹q¤l©ÒEDA²ÕºÓ¤h¯Z¦¨ÁZ²Ä¤@¦W
2006-09 ªL©¾½n, ¹q¤l©ÒEDA²ÕºÓ¤h¯Z¦¨ÁZ²Ä¤G¦W
2006-07 ³¯¬Ó¦t¡B½±±öªÚ¡B±iÄ£¤åÀò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (DAC2006) Paper title: Novel Full-Chip Gridless Routing Considering Double-Via Insertion
2006-07 ³ëªÃÂE¡B±iÄ£¤åÀò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (DAC2006) Paper title: Placement of Digital Microfluidic Biochips Using the T-tree Formulation
2006-07 ¦¿­õºû¡B±iÄ£¤åÀò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (ICCAD2006) Paper title: An Optimal Simultaneous Diode/Jumper Insertion Algorithm for Antenna Fixing
2006-07 ³¯ªF³Ç¡B¦¿­õºû¡B³\¤Ñ¹ü¡B³¯«H¦¨¡B±iÄ£¤åÀò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (ICCAD2006) Paper title: A High-Quality Mixed-Size Analytical Placement System for Large-Scale Circuit Designs
2006-07 §õ°ûµÓ¡B¼B§»¼Ý¡B±iÄ£¤åÀò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (ICCAD2006) Paper title: Voltage Island Partitioning and Floorplanning for Power Optimization Under Timing Constraints
2006-07 ¼B§»¼Ý¡BªL©¾½n¡B©P«äºÍ¡B±iÄ£¤åÀò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (ICCAD2006) Paper title: Current Path Analysis for Electrostatic Discharge Protection
2006-07 ¤è®a°¶¡BªL¨Ì¼ä¡B³ëªÃÂE¡B±iÄ£¤åÀò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (ICCAD2005) Paper title: A routing algorithm for flip chip design
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2006-04 ACM/IEEE Design Automation Conference (DAC2006) Paper title: Novel Full-Chip Gridless Routing Considering Double-Via Insertion ³¯¬Ó¦t¡B½±±öªÚ¡B±iÄ£¤å
2006-04 ACM/IEEE Design Automation Conference (DAC2006) Paper title: Placement of Digital Microfluidics Biochips Using the T-tree Formulation ³ëªÃÂE,·¨¨Î¬Â,±iÄ£¤å
2006-04 NTUplace Àò 2006 ACM/IEEE ISPD °ê»Ú¹q¤l³]­p¦Û°Ê¤Æ ¸m³nÅé ¬ãµoÄvÁɲĤT¦W (¤À¶µµû¤ñ: ¾É½uªø²Ä¤@¦W; ¾ãÅé«~½è²Ä¤G¦W [»P²Ä¤@¦W®t¶Z¤p©ó 1%]; ¾ãÅéÁ`¤À²Ä¤T¦W [»P²Ä¤@¦W®t¶Z¤p©ó 2%, »~®t½d³ò¤º]); ¬ãµo¹Î¶¤: ³¯ªF³Ç, ¦¿­õºû, ³¤Ñ¹ü, ³¯«H¦¨, ±iÄ£¤å
2006-04 ±iÄ£¤å±Ð±ÂÀò±o¥xÆW¤j¾Ç¡u±Ð¾ÇÀu¨}¼ú¡vAll-university Excellent Teacher Award, National Taiwan University, September 2006.
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2005-05 ACM/IEEE Design Automation Conference (DAC2005) Paper title: An Optimal Jumper Insertion Algorithm for Antenna Effect voidance/Fixing Authors:Ĭ¬f¿o,±iÄ£¤å
2005-05 ACM/IEEE Design Automation Conference (DAC2005) Paper title: Multilevel Full-Chip Routing for the X-Based Architecture (Best Paper Nomination) Authors:¦ó©v©ö,±i®f®p,±iÄ£¤å,³¯¤Ö³Ç
2005-04 NTUPlace¦b 2005 ISPD Placement Contest Àò±o°£¬ü°ê¥~²Ä¤@¦W¨ÎÁZ
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