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2011 1st Winner of 2011 IEEE CEDA PATMOS-TAC Contest

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2011 ºaÀò¹q¸ê¾Ç°|100¦~«×¾Ç³N°^Äm¼ú

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2011 ºaÀò99¦~«×°ê¬ì·|³Ç¥X¬ã¨s¼ú

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2010 The #1 worldwide in the citation ranking in the category of Hardware & Architecture in the Microsoft Academic Search Database link

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2010 Best Paper Awar in IEEE International Conference on Computer Design (ICCD2010) Paper title: Provably good OPC modeling and its applications to interconnect optimization

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2010 ºaÀò 2010 IBM Faculty Award

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2010 Best Paper Award of EDA Session in the 21th VLSI Design/CAD Symposium, Taiwan. Paper title: ECO Timing and Mask-Cost Optimization with Redundant Wires

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2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: Design-Hierarchy Aware Mixed-Size Placement for Routability Optimization

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2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: Native-Conflict-Aware Wire Perturbation for Double Patterning Technology (Best Paper Nominee)

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2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: High Variation-Tolerant Obstacle-Avoiding Clock Mesh Synthesis with Symmetrical Driving Trees

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2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: Template-Mask Design Methodology for Double Patterning Technology

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2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit Designs

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2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2010) Paper title: Redundant-Wires-Aware ECO Timing and Mask-Cost Optimization

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2010 ¤E¤Q¤K¾Ç¦~«×±Ð¨|³¡¥D¿ì¤j¾Ç®Õ°|¿nÅé¹q¸ô¹q¸£»²§U³]­p³nÅé»s§@ÄvÁÉ ©wÃD²Õ

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2010 ACM/IEEE Design Automation Conference (DAC2010) Paper title: Fast Timing-Model Independent Buffered Clock-Tree Synthesis

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2010 ACM/IEEE Design Automation Conference (DAC2010) Paper title: Pulsed-latch-aware placement for timing-integrity optimization

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Sangmin Kim
Youngsoo Shin
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2010 ACM/IEEE Design Automation Conference (DAC2010) Paper title: Cross-Contamination Aware Design Methodology for Pin-Constrained Digital Microfluidic Biochips

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2009 ºaÀò¡u¤¤°ê¹q¾÷¤uµ{¾Ç·|98¦~«C¦~½×¤å¼ú¡v

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2009 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009) Paper title: An Efficient Pre-assignment Routing Algorithm for Flip-Chip Designs

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Chung-Wei Lin
Yao-Wen Chang

2009 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009) Paper title: Simultaneous Layout Migration and Decomposition for Double Patterning Technology

Chin-Hsiung Hsu
Yao-Wen Chang
Sani R. Nassif

2009 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009) Paper title: Voltage-Drop Aware Analytical Placement by Global Power Spreading for Mixed-Size Circuit Designs

Yi-Lin Chuang
Po-Wei Lee
Yao-Wen Chang

2009 IEEE/ACM International Conference on Computer-Aided Design (ICCAD2009) Paper title: BIST Design Optimization for Large-Scale Embedded Memory Cores

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Wen-Chi Chao
Chien-Mo Li
Kuan-Yu Liao
Ming-Tung Chang
Min-Hsiu Tsai
Chih-Mou Tseng

2009 ¤E¤Q¤C¾Ç¦~«×±Ð¨|³¡¥D¿ì¤j¾Ç®Õ°|¿nÅé¹q¸ô¹q¸£»²§U³]­p³nÅé»s§@ÄvÁɤ£©wÃD²Õ

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2009 ACM/IEEE Design Automation Conference (DAC2009) Paper title: Spare-Cell-Aware Multilevel Analytical Placement

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2009 ACM/IEEE Design Automation Conference (DAC2009) Paper title: ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochip

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2009 ACM/IEEE Design Automation Conference (DAC2009) Paper title: Thermal-driven analog placement considering device matching

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2009 ACM/IEEE Design Automation Conference (DAC2009) Paper title: Flip-Chip Routing with Unified Area-I/O Pad Assignments for Package-Board Co-Design

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2009 Àò±o¡u97¾Ç¦~«×¥xÆW¿nÅé¹q¸ô»s³yªÑ¥÷¦³­­¤½¥qÃÙ§U¥x¤j¹q¤l©ÒEDA²Õ³Õ¤h¯Z¬ã¨s¥Í¼ú¾Çª÷¡v

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2009 Àò±o¥xÆW¤j¾Ç¹q¤l©Ò96¾Ç¦~«×³Ì¨Î³Õ¤h½×¤å¼ú

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2007 ¬ìªL½×¤å¼ú(Lam Thesis Award)

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2007 ICCAD Travel Grant Award

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2007 The 18th VLSI Design/CAD Symposium, Taiwan

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2007 ¨H¤å¤¯±Ð±Â¦~«×½×¤å¼ú

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2007 ACM/IEEE Design Automation Conference (DAC2007) Paper title: MP-trees: A Packing-Based Macro Placement Algorithm for Mixed-Size Designs

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2007 ACM/IEEE Design Automation Conference (DAC2007) Paper title: A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages

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2007 ACM/IEEE Design Automation Conference (DAC2007) Paper title: Analog Placement based on Novel Symmetry-Island Formulation

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2007 ACM/IEEE Design Automation Conference (DAC2007) Paper title: An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design (best paper nominee; received the highest score in the beyond-die track)

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2006 Àò±o¥xÆW¤j¾Ç¹q¤l©Ò2006¦~¡u¾Ç¥Í³Ç¥X¬ã¨s¼ú¡v

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2006 Àò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (ICCAD2006)
Paper title: A routing algorithm for flip chip design

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2006 Àò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (ICCAD2006)
Paper title: Current Path Analysis for Electrostatic Discharge Protection

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2006 Àò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (ICCAD2006)
Paper title: Voltage Island Partitioning and Floorplanning for Power Optimization Under Timing Constraints

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2006 ±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (ICCAD2006)
Paper title: A High-Quality Mixed-Size Analytical Placement System for Large-Scale Circuit Designs

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2006 Àò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (ICCAD2006)
Paper title: An Optimal Simultaneous Diode/Jumper Insertion Algorithm for Antenna Fixing

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2006 Àò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (DAC2006)
Paper title: Placement of Digital Microfluidic Biochips Using the T-tree Formulation

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2006 Àò±o«ä·½¬ì§Þ±Ð¨|°òª÷·| 2006¦~EDA¼úÀyª÷ (DAC2006)
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2006 ACM/IEEE Design Automation Conference (DAC2006) Paper title: Placement of Digital Microfluidics Biochips Using the T-tree Formulation

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2006 ACM/IEEE Design Automation Conference (DAC2006) Paper title: Novel Full-Chip Gridless Routing Considering Double-Via Insertion

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2005 Àò±o¡u»OÆW¤j¾Ç¾Ç¥Í³Ç¥Xªí²{¼ú¾Çª÷¡v

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2005 ACM/IEEE Design Automation Conference (DAC2005)
Paper title: An Optimal Jumper Insertion Algorithm for Antenna Effect voidance/Fixing

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2005 ACM/IEEE Design Automation Conference (DAC2005)
Paper title: Multilevel Full-Chip Routing for the X-Based Architecture (Best Paper Nomination)

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2004 ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004)
Paper title: Temporal floorplanning using 3D-subTCG (Best Paper Nomination)

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2004 ¥xÆW¤j¾Ç±Ð¾ÇÀu¨}¼ú
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2004 «ä·½¬ì§Þ±Ð¨|°òª÷·| DAC½×¤å¼ú :
Paper title:Efficient Power/Ground Network Analysis for Power Integrity-Driven Design Methodology

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2004 °ê¬ì·|²Ä¤T©¡¡]93¦~«×¡^§d¤j·ß¬ö©À¼ú

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2003 ACM Transactions on Design Automation of Electronic Systems (TODAES) --Rectilinear block placement using B*-trees (Nomination for Best Paper Award )

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2002 ¤¤°ê¹q¾÷¤uµ{¾Ç·|«C¦~½×¤å¼úºÓ¤h½×¤å Thesis title: A Novel Framework for Multilevel Routing Considering Routability and Performance

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2002 The 13th VLSI Design/CAD Symposium
Paper title: Integrating Buffer Planning with Floorplanning for Simultaneous Area, Timing, Noise, and Congestion Optimization (Highest Score)

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2002 IEEE/ACM International Conference on Computer-Aided Design (ICCAD'02) Paper title: A Novel Framework for Multilevel Routing Considering Routability and Performance (Best Paper Nomination)

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2001 The 12th VLSI Design/CAD Symposium
Paper title: A P-admissible non-slicing floorplan representation with a worst-case linear-time packing scheme
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2001 ±Ð¨|³¡¥D¿ì¤j¾Ç®Õ°|¿nÅé¹q¸ô¹q¸£»²§U³]­p³nÅé»s§@ÄvÁÉ-©wÃD²Õ

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2001 IEEE International Conference on Computer Design (ICCD'01) CAD Track
Paper title: Generic ILP-based approaches for dynamically reconfigurable FPGA partitioning (Highest Score)

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2001 ¡]­º©¡¡^°ê®a¬ì¾Ç©e­û·|ºÓ¤h½×¤å¼ú
Thesis title: Performance-driven modeling and optimization under the transmission-line delay model


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2000 ACM/IEEE Design Automation Conference (DAC'2K)
Paper title: B*-trees: A New Representation for Nonslicing Floorplans (Best Paper Nomination)

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2000 The 11th VLSI Design/CAD Symposium
Paper title: Simultaneous wire sizing and buffer insertion/sizing with applications to interconnect-driven floorplanning (³Ì¨Î¾Ç¥Í
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1999 EE Time Citation
Paper title: Universal switch blocks for three-dimensional FPGA design

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1998 ¤¤°ê¹q¾÷¤uµ{¾Ç·|«C¦~½×¤å¼úºÓ¤h½×¤å
Thesis title: Matching-based Algorithms for FPGA Segmentation Design

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1996 ACM International Aymposium on Field-Programmable Gate Arrays (FPGA'96)
Paper title: Universal switch-module design for symmetrical-array-based FPGAs (Highest Score)

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1995 IEEE International Conference on Computer Design (ICCD'95)
Paper title: FPGA global routing based on a new congestion metric (Best Paper Award)

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