Huang-Yu Chen (陳皇宇), Ph.D. (biography)


 

CONTACT INFORMATION
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Manager

E-mail: yellowestfish{at}gmail.com

Design and Technology Platform
Research and Development
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC)
8, Li-Shin Rd. 6, Hsinchu Science Park
Hsinchu, Taiwan 300-78

 

EDUCATION
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RESEARCH INTERESTS
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PUBLICATIONS
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Disclaimer: Many papers below are available for easy access. However, please be aware that all papers are copyrighted by the organization responsible for the corresponding conference or journal.
EXPERIENCES (Selected)
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  • Manager, Test Chip Implementation Department (TCID), System and Chip Design Solutions Development Division, Design and Technology Platform, R&D, TSMC, Taiwan, Mar. 2017--present.
  • Technical Manager, Test Chip Development Department (TCDD-2), System and Chip Design Solutions Development Division, Design and Technology Platform, R&D, TSMC, Taiwan, Feb. 2016--Mar. 2017.
  • Session Chair, "Don't Fret About Your FinFET: Physical Design in 14nm and Beyond," Design Automation Conference (DAC), Austin, TX, USA, Jun. 4, 2013. (certif.)
  • Technical Manager, Embedded System Program (ESP), Test Chip Design and Validation Division, Design and Technology Platform, R&D, TSMC, Taiwan, Jul. 2012--Jan. 2016.
  • Technical Manager, Design Flow Department I (DFD-1), Design Methodology Division, Design and Technology Platform, R&D, TSMC, Taiwan, Jun. 2010--Jun. 2012.
  • Principal Engineer, Reference Design Flow Developement Department (RDFDD), Design Methodology Division, Design and Technology Platform, R&D, TSMC, Taiwan, Mar. 2009--May. 2010.
  • Research Assistant, TSMC, project "Design, Manufacturing, and Testing (DMT) for Sub-wavelength ULSI Rapid Yield Ramp," Aug. 2008--Feb. 2009.
  • Research Assistant, National Science Council, Taiwan, Aug. 2007-Jul. 2008, Project "Manufacturability and Reliability for Nanometer Technologies and Physical Design Challenges" (國科會奈米IC設計之前瞻電子設計自動化技術--子計畫五:在奈米製程下考量可 製造性和可靠度之實體設計) (96-2628-E-002-248-MY3)
  • Research Assistant, UMC, project "Physical Design for Nanometer IC Design," Oct. 2004--Oct. 2007.

HONORS & AWARDS (Selected)
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  • Outstanding Procedural Innovation Award, "S.M.A.R.T: 1st DTP Cross-Design/Technology Design Analysis Platform," DTP, TSMC, 2016/Q2.
    (台積電設計法則處2016/Q3傑出創新獎) (4 awards out of 16 innovations)(highest score)
  • Outstanding Procedural Innovation Award, "Automatic Macro FP Migration through Different Technology," DTP, TSMC, 2016/Q2.
    (台積電設計法則處2016/Q2傑出創新獎) (3 awards out of 13 innovations)
  • Best Paper Award, DTP conference, TSMC, 2013. (certif.)
    (台積電設計法則處2013最佳論文獎) (4 awards out of 56 submissions)
  • Outstanding Procedural Innovation Award, "Using PPA-Efficient Cells for High-Quality Chip Implementation," DTP, TSMC, 2013/Q2. (certif.)
    (台積電設計法則處2013/Q2傑出創新獎) (4 awards out of 36 innovations)
  • Outstanding Patent Award, "Onion-Like Methods for Self-Aligned-Double-Patterning-Compliant Standard Cell Design," DTP, TSMC, 2012/Q4. (certif.)
    (台積電設計法則處2012/Q4傑出專利獎) (3 awards out of 76 patents)
  • Outstanding Procedural Innovation Award, "Fast and Robust Performance-aware Circuit Evaluation Platform," DTP, TSMC, 2012/Q3. (certif.)
    (台積電設計法則處2012/Q3傑出創新獎) (4 awards out of 31 innovations)
  • Outstanding Procedural Innovation Award, "Automatic Standard Cell Driving Strength Enrichment," DTP, TSMC, 2012/Q1. (certif.)
    (台積電設計法則處2012/Q1傑出創新獎) (4 awards out of 24 innovations)
  • Outstanding Procedural Innovation Award, "N20 DPT Full-Chip Easy-to-Fix Smart Highlight for Long-Range G0 Odd Loops," DTP, TSMC, 2011/Q3. (certif.)
    (台積電設計法則處2011/Q3傑出創新獎) (4 awards out of 28 innovations)
  • Outstanding Patent Award, "Methods of Cell-Abutting Conflict Removal for Multiple Patterning Technology," DTP, TSMC, 2010/Q4. (certif.)
    (台積電設計法則處2010/Q4傑出專利獎) (5 awards out of 59 patents)
  • Outstanding Procedural Innovation Award, "Random Pattern Generator and Metal Fill for N14/N20 MEEP Technology," DTP, TSMC, 2010/Q3. (certif.)
    (台積電設計法則處2010/Q3傑出創新獎) (3 awards out of 42 innovations)
  • Winner of R&D idea forum, TSMC, 2010/Q2.
  • TSMC 2009 Special Award. (certif.)
    (台積電2009特別貢獻獎) (94 awards out of 28000+ TSMC colleagues)
  • Outstanding Patent Award, "Practical Routing Rules for Generating DPT-friendly Layout Patterns," DTP, TSMC, 2009/Q4. (certif.)
    (台積電設計法則處2009/Q4傑出專利獎)
  • Outstanding Procedural Innovation Award, "GDSII-to-LEF/DEF Transformation," DTP, TSMC, 2009/Q3. (certif.)
    (台積電設計法則處2009/Q3傑出創新獎) (3 awards out of 32 innovations)
  • Outstanding Patent Award, "Methods for Chip-Level Shrink ECO," DTP, TSMC, 2009/Q2. (certif.)
    (台積電設計法則處2009/Q2傑出專利獎)
  • Honorary Member, the Phi Tau Phi Scholastic Honor Society, Jun. 2009. (certif.)
    (中華民國斐陶斐榮譽學會會員)
  • GIEE Annual Award, Jan. 2009. (certif.)
    (台灣大學電子所年度榮譽獎)
  • NTU Outstanding Scholarship, Dec. 2008. (certif.)
    (台灣大學傑出表現獎學金)
  • Best Paper Award, the 19th VLSI Design/CAD Symposium, Taiwan, Aug. 2008. (3 awards out of 297 submissions) (certif.)
    (第十九屆台灣超大型積體電路設計暨計算機輔助設計技術研討會最佳論文獎)
  • The 2nd Place, 2008 ACM ISPD Global Routing Contest. (certif.)
    (2008 ACM ISPD 國際全域繞線競賽亞軍) (台大校訊921期) (NTUgr team)
  • National Contestant, Domestic CADathlon Competition, Ministry of Education, Taiwan, 2007.
    (台灣代表隊,參加2007年國際 ACM CADathlon at ICCAD 競賽)
  • The 2nd Rank Student Award, Group EDA, Graduate Institute of Electronics Engineering, NTU, 2007.
    (台灣大學電子所EDA組博士班成績第二名)
  • Best Paper Nominee, IEEE/ACM International Conference on Computer-Aided Design, 2007. (9 nominations out of 510 submissions)
    (ICCAD-2007 最佳論文獎提名) (台大校訊902期)
  • The 7th Place, 2007 ACM ISPD Global Routing Contest.
    (2007 ACM ISPD 國際全域繞線研發競賽第七名)
  • OKWAP Educational Scholarship, 2007.
    (英華達品學兼優教育獎學金)
  • Outstanding Research Award, Graduate Institute of Electronics Engineering, NTU, 2006. (certif.)
    (台灣大學電子所學生傑出研究獎)
  • The 1st Rank Student Award, Group EDA, Graduate Institute of Electronics Engineering, NTU, 2006.
    (台灣大學電子所EDA組博士班成績第一名)
  • TSMC NTU-EDA Fellowship for Ph.D. Student, 2005. (the 1st recipient of the TSMC NTU-EDA Fellowship for Ph.D. student)
    (台積電台大電子所EDA組博士班研究生獎學金)
  • The 1st Rank, EDA Ph.D. Program Entrance Competition, Graduate Institute of Electronics Engineering, NTU, 2005.
    (台灣大學電子所EDA組博士班直升第一名)
  • The 1st Rank Student Award, Graduate Institute of Electronics Engineering, NTU, 2005. (certif.) (the #1 rank out of more than 400 NTU-EE master students)
    (台灣大學電子所ICS組及電機學群碩士班成績第一名)
  • The 3rd Prize, IC/CAD Contest, Ministry of Education, 2005.
    (教育部主辦大學校院積體電路電腦輔助設計軟體製作競賽定題組佳作)
  • The 3rd Rank in the final grade (top 5.88% of the students), Dept. of EE, NTHU. (certif.)
    (清華大學電機系畢業成績第三名)

SPECIAL SKILLS & EXPERTISES
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  • C/C++ programming
  • OpenAccess/GDSII/LEF/DEF/.lib db knowledge
  • Deep learning
  • TCL/Python/R/Matlab/Maple/WX/Gnuplot scripting
  • EDA tools
    • Cadence Innovus (certif.)
    • Dorado Tweaker
    • Mentor Graphics Calibre rules writing (DRC & LVS) (certif.)
    • Synopsys IC Compiler (certif.) and Prime Time (certif.)
  • PHP/MySQL database systems
  • Linux/Unix/Windows operating systems

NEWS COVERAGE
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  1. 台大校訊902期, "臺大團隊再創佳績 繼ISSCC之後ICCAD以9篇論文領先產學界位居全球之冠," Dec. 19, 2007
    "臺大獲得最佳論文獎提名的兩篇論文分別是電子所/電機系...張耀文教授的團隊,學生成員為陳皇宇、周思睿、王聖龍。"
  2. EE Times Coverage, "Future of chip design revealed at ISPD," Apr. 17, 2008.
    "how the Taiwanese beat both the U.S. and Europeans in the ISPD Global Routing Contest."
  3. 台大校訊921期, 台大電機之友30期, "臺大電子所/電機系研究團隊勇奪ACM/IEEE ISPD 2008國際全域繞線研發競賽亞軍," May 21, 2008.
    "在美國奧瑞岡州波特蘭市閉幕的「ACM/IEEE ISPD 2008國際全域繞線競賽」(ACM/IEEE ISPD 2008 Global Routing Contest),臺大電子所與電機系張耀文教授和電子所博士生陳皇宇與許欽雄所研發的NTUgr全域繞線器獲得了亞軍的榮耀,打敗其他來自美洲、歐洲、中國大陸(香港)等地區共九隊決賽隊伍"
  4. 台大電機之友30期, "陳皇宇等二名同學榮獲第十九屆台灣超大型積體電路設計暨計算機輔助設計技術研討會CAD組最佳論文獎", Dec. 2008.

WEB ACTIVITY
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PHOTOS
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Last update: 2016-12-13