Electronic Design Automation Lab.
Graduate Institute of Electronics Engineering
National Taiwan University
No.1, Sec.4, Roosevelt Rd. Taipei, Taiwan, 10617, R.O.C.

 
 
Tel: +886-2-23635251 ext. 6406
Fax: +886-2-23681679
Mobile: +886-922-271858

E-mail: lizarde@lina.ee.ntu.edu.tw
 
Tsung-Yi Ho

Current Status:        

                           Assistant Professor, Department of Computer Science and Information Engineering , National Cheng Kung University

 

Education:        

                           2001-2005       PhD,

                                                    Electrical Engineering Dept.

                                                    National Taiwan University.

 

                           1999-2001       Master,

                                                    Computer Information Science Dept.

                                                    National Chiao-Tung University.

 

Research Interests:

                   VLSI design automation, architectures, and systems (with emphasis on physical design for nanometer IC technologies and SoC integration)

                   Multilevel routing algorithms considering nanometer electrical effects

 

Related Publications:

                   1. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "A Fast Crosstalk-Driven Multilevel Routing System," The 14th VLSI

                      Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2003.

 

                   2. T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee, "A Fast Crosstalk- and Performance-Driven Multilevel

                      Routing System," Proceedings of IEEE/ACM International Conference on Computer-Aided Design

                      (ICCAD-2003), San Jose, CA, Nov. 2003.

 

                   3. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "Multilevel Routing with Antenna Avoidance,"

                      Proceedings of ACM International Symposium on Physical Design (ISPD-2004), Phoenix, AZ,

                      April, 2004.

 

                   4. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "Multilevel Routing with Jumper Insertion for Antenna Avoidance,"

                      Proceedings of IEEE International SOC Conference (SOCC-2004), Santa Clara, CA, September, 2004.

 

                   5. T.-Y. Ho, C.-F. Chang, Y.-W. Chang, and S.-J. Chen, "Multilevel Full-Chip Routing for the X-Based Architecture,"

                      Proceedings of IEEE/ACM Design Automation Conference (DAC-2005), Anaheim, CA, June, 2005 (Nominated for Best Paper).

 

                   6. C.-F. Chang, T.-Y. Ho, and Y.-W. Chang, "XRoute: a multilevel routing system for the X-based architecture,"

                      The 16th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2005.

 

                   7. C.-F. Chang, T.-Y. Ho, and Y.-W. Chang, " XRoute: An X-Architecture Full-Chip Router Based on a Novel Multilevel Framework,"

                      submitted to IEEE/ACM Design Automation Conference (DAC-2006).

 

                   8. T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee, "Crosstalk- and Performance-Driven Multilevel Full-Chip Routing

                      ," IEEE Trans. Computer-Aided Design, June 2005.

 

                   9. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "Multilevel Routing with Jumper Insertion for Antenna Avoidance

                      ," accepted and to appear in Integration: The VLSI Journal, (EI/SCI).

 

                   10. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, "Multilevel Routing with Antenna Avoidance

                       ," in revision, IEEE Trans. Computer-Aided Design.

 

                   11. T.-Y. Ho, C.-F. Chang, Y.-W. Chang, and S.-J. Chen, "Multilevel Full-Chip Routing for the X-Based Architecture,"

                       ," in revision, IEEE Trans. Computer-Aided Design.

 

                   12. S.-J. Chen and T.-Y. Ho, "A New Interconnect Architecture: X-Architecture," Component Magazine, Jan. 2005.(invited article)

 

                   13. T. Y. Ho, Y. W. Chang, and S. J. Chen, "Multi-Level Routing with Antenna Avoidance," Bulletin of the College of Engineering, NTU,

                       No. 93, pp. 51-61, Feb. 2005.

 

Academic Honors:

                   1. Best Thesis Award, Institute of Information and Computing Machinery, 2005.

                   2. Lam Research Thesis Award, 2005.

                   3. Acer Long-Term Thesis Award, 2005.

                   4. Best Paper Nomination (IEEE/ACM Design Automation Conference), 2005.

                   5. SpringSoft Scholarship for DAC Regular Paper, 2005.

                   6. ACM SIGDA PhD Forum at DAC (1st PhD student of Taiwan received this honor), 2005.

                   7. SpringSoft Scholarship for PhD Forum at DAC, 2005.

                   8. ACM SIGDA PhD Forum at ASPDAC, 2005.

                   9. SpringSoft Scholarship for PhD Forum at ASPDAC, 2005.

                   10. SIGDA/DAC University Booth at DAC conference, 2004.

                   11. SpringSoft EDA Scholarship for University Booth at DAC conference, 2004.

                   12. The 2nd Place in the IC/CAD Contest, Ministry of Education, 2003.

                   13. SIGDA/DAC University Booth at DAC conference, 2003.

                   14. EDA PhD Forum at VLSI/CAD Symposium, 2003.

                   15. Lecturer, Computer-Aided System Design in GIEE, NTU, 2003.

                   16. The 1st Place in the IC/CAD Contest, Ministry of Education, 2002.

                   17. Visiting Scholar, ECE Dept. at University of California, Santa Barbara, 2003-2004 (with Prof. Malgorzata Marek-Sadowska).

                   18. Visiting Scholar, IPS Dept. at Waseda University, Kitakyushu, 2005 (with Prof. Satoshi Goto and Prof. Takeshi Yoshimura).