Tung-Chieh Chen
Ph.D. Candidate

E-mail: donnie {at} eda.ee.ntu.edu.tw

The Electronic Design Automation Lab.
Graduate Institute of Electronics Engineering
BL 406, National Taiwan University
No.1, Sec. 4, Roosevelt Road
Taipei, Taiwan, 10617, R.O.C.


陳東傑
博士候選人

E-mail: donnie {at} eda.ee.ntu.edu.tw

電子設計自動化實驗室
電子工程學研究所
10617台北市大安區羅斯福路四段一號
台灣大學博理館406
 

Education
  • 2004-2008:
    Ph.D. Candidate,
    Graduate Instituteof Electronics Engineering,
    National Taiwan University
  • 2003-2004:
    M.S. program,
    (approved for the entrance into Ph.D. program directly in 2004)
    Dept. of Electrical Engineering,
    National Taiwan University
  • 1999-2003:
    B.S.,
    Dept. of Electrical Engineering,
    National Taiwan University

Research Interests

  • Electronics design automation (with emphasis on physical design for nanometer IC technologies and SoC integration)
  • Large-scale mixed-size floorplanning/placement
  • Congestion-driven, timing-driven, and power-aware placement
  • Download NTUplace VLSI placement tool (link) -- You need to register first.

Publications
  • ACM/IEEE Journal Paper
    1. T.-C. Chen and Y.-W. Chang, "Modern Floorplanning Based on B*-trees and Fast Simulated Annealing," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD) , vol. 25, no. 4, pp. 637--650, Apr. 2006.
    2. T.-C. Chen, Y.-W. Chang, and S.-C. Lin, "A new multilevel framework for large-scale interconnect-driven floorplanning," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 2, pp. 286--294, 2008.
    3. T.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, "Effective wire models for X-architecture placement," in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 27, no. 4, pp. 654--658, 2008.
    4. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen and Y.-W. Chang, "NTUplace3: An analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints," accepted and to appear in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2008 .
    5. T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Liu, and D. Liu, " MP-trees: a packing-based macro placement algorithm for modern mixed-size designs," accepted and to appear in IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2008.
  • Other Conference Papers
    1. T.-C. Chen and Y.-W. Chang, "Fast simulated annealing and its applications modern floorplanning problems," in Proc. of the 15th VLSI Design/CAD Symposium, Pingdon, Taiwan, Aug. 2004.
    2. T.-C. Chen and Y.-W. Chang, "A new multilevel framework for large-scale interconnect-driven floorplanning," in Proc. of the 16th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2005.
    3. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen and Y.-W. Chang, "A novel analytical mixed-size placement algorithm considering preplaced blocks," in Proc. of the 17th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2006.
    4. T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, and D. Liu, "A macro placer based on a new packing representation," in Proc. of the 17th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2006.
  • Book Chapters
    1. Y.-W. Chang, T.-C. Chen, and H.-Y. Chen, "Chapter 9: Physical Design for System-On-a-Chip," in Essential Issues in SOC Design: Designing Complex Systems-on-Chip (Y.-L. Lin, Editor), John Wiley & Sons, 2006 (invited article). (Amazon) (ISBN: 1402053517)
    2. T.-C. Chen and Y.-W. Chang, "Packing Floorplan Representation,'' Handbook of Algorithms for Physical Automation (C. Alpert, D. Mehta, and S. Sapatnekar, Editors), CRC Press, 2007 (invited article). (Amazon) (ISBN: 0849372429)
    3. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, "Chapter 11: NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs," in Modern Circuit Placement: Best Practices and Results (G.-J. Nam and J. Cong, Editors), Springer, 2007 (invited article). (Amazon) (ISBN: 038736837X)
    4. T.-C. Chen and Y.-W. Chang, "Chapter 10: Floorplanning," in Electronic Design Automation: Synthesis, Verification, and Testing (L.-T. Wang, Y.-W. Chang, and K.-T. Cheng, editors), Elsevier/Morgan Kaufmann, 2008.

Experiences
  • Visiting Scholar, ECE Department, University of Texas at Austin, Jan 2007 -- Dec 2007.
  • Research Assistant, SpringSoft Corp., Aug. 2006 -- Dec. 2006
    Project "Manufacturability-Aware Physical Design for Large-Scale VLSI Circuits"
  • Research Assistant, National Science Council, Taiwan, Sep. 2005 -- Dec. 2006
    Project "Physical Integration for Trillion-Transistor Scaled System-on-Chip"
    (兆級晶片系統前瞻技術研究--子計畫六：兆級晶片系統實體整合之研究)
    (94-2215-E-002-030, 95-E-2221-E-002-372)
  • Research Assistant, MediaTek Inc., Apr. 2005 -- Mar. 2006
    Project "Large-Scale Mixed-Size Macro/Cell Placement"
  • Research Assistant, SpringSoft Corp., Oct. 2003 -- Sep. 2004
    Project "Floorplanning and Routing for Full-Custom IC Design"
  • Web Application Developer, NTUEE Online Office, Oct. 2003 -- Dec. 2006
  • Web Developer/Maintainer, Industrial Technology R&D Master Program, NTU, July 2006 -- Dec. 2006
  • English-Chinese Translator, Garmin, Nov. 2004 -- Jan. 2005
  • Teaching Assistant, Electronic Design Automation, Dept. of EE, Spring 2004
  • Teaching Assistant, Algorithm, Dept. of EE, Fall 2003
  • Administration Staff, The 2nd EDA Workshop, E-Land, Taiwan, July, 2006
  • Administration Staff, The 1st EDA Workshop, Yunlin, Taiwan, July, 2005
  • Administration Staff, The 15th VLSI Design/CAD Symposium, Pingdon, Taiwan, Aug. 2004

Honors
  • Contest
    • The 3rd Place, ACM/ISPD & IEEE/CEDA Placement Contest, 2006
    • The 7th Place, ACM/ISPD Placement Contest, 2005
    • The 1st Place, ACM SIGDA CADathlon at ICCAD, 2007 台大校訊
    • The 3rd Place, ACM SIGDA CADathlon at ICCAD, 2006
    • The 4th Place, ACM SIGDA CADathlon at ICCAD, 2005
    • The 1st Prize, IC/CAD Contest, Ministry of Education, 2006
    • The 3rd Prize, IC/CAD Contest, Ministry of Education, 2005
    • The 3rd Prize, IC/CAD Contest, Ministry of Education, 2004
    • The 1st Prize, IC/CAD Contest, Ministry of Education, 2003 (The 1st place in 75 teams.)
    • The 1st Prize, Lam Thesis Award, 2003 (科林論文獎)
    • 佳作, 最佳美工獎, 最佳票選獎, 電信加值軟體大賽跨網路組, Oct 2003.
    • The 1st Prize, Electronics Innovation Award, SoC Center, NTU, Nov 2003 (電子創新設計競賽)
    • The 1st Prize, Mobileheroes, Industrial Development Bureau, 2003 (無線通訊競賽)
    • Intel Innovation Award, Industrial Development Bureau/MOEA and Intel Microelectronics Asia Ltd., Taiwan Branch, Oct 2003 (Intel創新研究獎)
    • Society Welfare Leadship Award, TIC100 Technology Innovation Competition, Advantech Foundation, Dec. 2001--Aug. 2002
    • The 2nd Prize, Applied Sciences, National Primary and High Schools Science Fair, 1998
  • Scholarship/Travel Grant
    • Ph.D. Scholarship, NTU-MTK Wireless Communication Research Project, 2006
    • NTUEE Class A Scholarship, Fall 2003, Spring 2004, Fall 2004, Spring 2005, Fall 2005
    • Travel Grant, Foundation for the Advancement of Outstanding Scholarship, 2005
    • SpringSoft EDA Scholarship for DAC UBooth 2005, ICCAD-2005 Paper, ASPDAC Ph.D. Forum 2006, ICCAD-2006 Paper, DAC-2007 Paper
    • Educational Scholarship from OKWAP, 2005 (公益信託英華達OPWAP教育基金)
    • Garmin Scholarship, 2004 (台灣國際航電獎學金)
    • NTU Outstanding Scholarship, Dec 2003 (國立台灣大學傑出表現獎學金 才藝類)
    • Computer Society of the Republic of China Scholarship, 2003 (中華民國電腦學會獎學金)
    • 台北市建築開發商業同業公會 獎學金, Nov 2001
    Other
    • Invited Speaker, Graduate Student Forum at 17th VLSI Design/CAD Symposium, 2006
    • Ph.D. Forum at IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC), 2006
    • ACM SIGDA/DAC University Booth at DAC, 2004, 2005
    • The 2nd Rank, ICS/CS Ph.D. Program Entrance Competition, 2004
    • The 1st Rank, CS Group Graduate Program Entrance Competition, Dept. EE, 2003 (台大電機所CS組碩士甄試入學榜首)
    • The Presidential Award, National Taiwan University, Fall 2002 (台大書卷獎)

 

 Last Update: April 23, 2008