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Thesis |
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標題: |
Routing Architectures and Algorithms for Field-Programmable Gate Arrays |
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標題: |
Routability Optimization with Buffer Planning in Floorplan Design |
出版單位: |
The Chinese University of Hong Kong | 年份: |
2002 |
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標題: |
Placement with Boundary Constraints Using B*-tree |
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標題: |
Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning |
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標題: |
Sequence-Pair Based Floorplanning |
出版單位: |
交大資科所 | 年份: |
1999 | 備註: |
2本 |
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標題: |
Design and Analysis of Universal Switch Blocks for Hierarchical FPGAs |
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標題: |
Matching-based Algorithms for FPGA segmentation Design |
出版單位: |
交大資科所 | 年份: |
1998 | 備註: |
2本 |
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標題: |
Using Branch-and-Bound Strategy to Approach Scheduling Problem in High-Level Synthesis |
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標題: |
Implementation of a Timing-Driven FPGA Router |
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標題: |
An Architecture-Driven Metric for Simultaneous Placement and Global Routing for FPGAs |
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標題: |
Architectures and CAD for Dynamically Reconfigurable Field-Programmable Gate Arrays |
出版單位: |
交大資科所 | 年份: |
2000 | 備註: |
2本 |
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標題: |
B*-Tree: A New Representation for Non-Slicing Floorplans |
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標題: |
Formula for Performance Optimazation with Applications to Interconnect-Driven Floorplanning |
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標題: |
Multilevel Large-scale Module Placement/Floorplanning |
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標題: |
A Novel Framework for Multilevel Routing Considering Routability and Performance |
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標題: |
Integrating Buffer Planning with Floorplanning for Simultaneous Area, Timing, Noise, and Congestion Optimization |
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標題: |
Interconnect-driven Floorplanning |
出版單位: |
The Chinese University of Hong Kong | 年份: |
2002 |
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標題: |
Interconnect Optimization for Deep Submicron Technology |
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標題: |
Global Router Combined with Buffer-Insertion for SOC Design Automation |
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標題: |
Temporal Floorplanning Using 3D-subTCG |
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標題: |
Fast Power/Ground Distribution Network Synthesis for Signal Integrity-Driven Floorplanning |
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標題: |
Placement with an Optimal Evaluation Scheme for Alignment and Performance Constraints |
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標題: |
Accurate Delay Modeling for Bufferd RLY/RLC Trees |
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標題: |
Simultaneous Floorplanning and Power/Ground Network Synthesis |
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標題: |
Block and Input/Output Buffer Placement in Flip-chip Design |
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標題: |
Termal-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing |
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標題: |
Performance-Drvien Routing-Tree Construction with Obstacle Consideration |
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標題: |
Floorplan and Power/Ground Network Co-Synthesis |
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標題: |
Performance-Driven Block and Input/Output Buffer Placement in Flip-Chip Design |
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標題: |
A Surface Integral Impedance Extraction for General Interconnect Structure |
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標題: |
A Novel Framework for Multilevel Routing Considering Routability and Performance |
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標題: |
Multilevel Large-scale Module Placement/Floorplanning |
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|
標題: |
Formula for Performance Optimazation with Applications to Interconnect-Driven Floorplanning |
|
|
標題: |
B*-Tree: A New Representation for Non-Slicing Floorplans |
|
|
標題: |
Architectures and CAD for Dynamically Reconfigurable Field-Programmable Gate Arrays |
出版單位: |
交大資科所 | 年份: |
2000 | 備註: |
2本 |
|
|
標題: |
An Architecture-Driven Metric for Simultaneous Placement and Global Routing for FPGAs |
|
|
標題: |
Implementation of a Timing-Driven FPGA Router |
|
|
標題: |
Using Branch-and-Bound Strategy to Approach Scheduling Problem in High-Level Synthesis |
|
|
標題: |
Matching-based Algorithms for FPGA segmentation Design |
出版單位: |
交大資科所 | 年份: |
1998 | 備註: |
2本 |
|
|
標題: |
Design and Analysis of Universal Switch Blocks for Hierarchical FPGAs |
|
|
標題: |
Sequence-Pair Based Floorplanning |
出版單位: |
交大資科所 | 年份: |
1999 | 備註: |
2本 |
|
|
標題: |
Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning |
|
|
標題: |
Placement with Boundary Constraints Using B*-tree |
|
|
標題: |
Routability Optimization with Buffer Planning in Floorplan Design |
出版單位: |
The Chinese University of Hong Kong | 年份: |
2002 |
|
|
標題: |
Routing Architectures and Algorithms for Field-Programmable Gate Arrays |
|
|
標題: |
Integrating Buffer Planning with Floorplanning for Simultaneous Area, Timing, Noise, and Congestion Optimization |
|
|
標題: |
Interconnect-driven Floorplanning |
出版單位: |
The Chinese University of Hong Kong | 年份: |
2002 |
|
|
標題: |
Interconnect Optimization for Deep Submicron Technology |
|
|
標題: |
Global Router Combined with Buffer-Insertion for SOC Design Automation |
|
|
標題: |
Temporal Floorplanning Using 3D-subTCG |
|
|
標題: |
Fast Power/Ground Distribution Network Synthesis for Signal Integrity-Driven Floorplanning |
|
|
標題: |
Placement with an Optimal Evaluation Scheme for Alignment and Performance Constraints |
|
|
標題: |
Accurate Delay Modeling for Bufferd RLY/RLC Trees |
|
|
標題: |
Simultaneous Floorplanning and Power/Ground Network Synthesis |
|
|
標題: |
Block and Input/Output Buffer Placement in Flip-chip Design |
|
|
標題: |
Termal-Driven Interconnect Optimization by Simultaneous Gate and Wire Sizing |
|
|
標題: |
Performance-Drvien Routing-Tree Construction with Obstacle Consideration |
|
|
標題: |
Floorplan and Power/Ground Network Co-Synthesis |
|
|
標題: |
Performance-Driven Block and Input/Output Buffer Placement in Flip-Chip Design |
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標題: |
A Surface Integral Impedance Extraction for General Interconnect Structure |
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標題: |
An RDL Routing System for Flip-Chip Design |
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標題: |
Msigma: a Multilevel Full-Chip Routing System Considering SIGnal-integrity and Manufacturability |
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標題: |
Floorplan and Power/Ground Network Co-Synthesis for Fast Design Convergence |
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標題: |
Xroute: An X-Architecture Full-Chip Router Based on a Novel Multilevel Framework |
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標題: |
A Detailed Placement Algorithm for Large-Scale VLSI Circuits |
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標題: |
Post-Layout Double-Via Insertion for Yield Enhancement |
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標題: |
Statistical Thermal- and Timing-Constrained Circuit Optimization |
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標題: |
ECO Timing Optimization Using Spare Cells and Technology Remapping |
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標題: |
Efficient Obstacle-Avoiding Rectilinear Steiner Tree Construction |
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標題: |
A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages |
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標題: |
A High-Quality Transitive-Closure-Graph-Based Macro Placer |
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標題: |
Dummy Metal Insertion Based on Density Gradient Minimization with Coupling Constraints |
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標題: |
Synthesis of Digital Microfluidic Biochips: Modeling, Placement, and Routing |
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標題: |
Modern VLSI Floorplanning and Placement Considering Performance and Manufacturability |
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標題: |
Floorplan and Power/Ground Network Co-Synthesis for Mutiple Supply Voltage Designs |
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標題: |
An Effective Power Management Flow in MTCMOS Design |
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標題: |
Routing for Analog Integrated Circuits |
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標題: |
Statistical Circuit Optimization using Simultaneous Gate and Wire Sizing |
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標題: |
Interconnect Optimization Considering Optical Proximity Correction |
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標題: |
A Multiple-Suply-Voltage Design Flow from Voltage Assignment to Floorplan |
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標題: |
Modern VLSI Routing Considering Reliability and Manufacturability |
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標題: |
Routing Algorithm for Chip-Package-Board Co-Design |
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標題: |
Hierarcahical Analog Circuit Placement |
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標題: |
VLSI Placement Considering Routability, Performance, and Reliability |
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標題: |
Native-Conflict-Aware Wire Perturbation for Double Patterning Technology |
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標題: |
Lithography Friendly Mutilevel Analytical Placement |
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標題: |
Redundant-Wires-Aware ECO Timing and Mask Cost Optimization |
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標題: |
A Unified Droptlet Manipulation Algorithm on Cross-Referencing Microfluidic Biochips |
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標題: |
Design Methodology for Digital Microfluidic Biochips Considering Pin-Count Reduction and Cross-Contamination Avoidance |
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標題: |
Blockage-Avoiding Beffered Clock-Tree Synthesis with Clock Latency-Range Minimization |
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標題: |
Routing Algorithm for Flip-Chip Designs |
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標題: |
Gate-Level Cost Evaluation for Three-Dimensional Integrated Circuits |
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標題: |
Design Methodology for Double Patterning Technology |
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標題: |
An Automatic Optical-Simmulation-Based Lithography Hotspot Fix Flow for Post-Route Optimization |
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標題: |
A New Chip-Package-Board Codesign Methodology |
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標題: |
Analog Placement with Symmtery and Regularity Considerations |
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標題: |
VLSI Placement Considering Routability and Power Consumption |
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標題: |
Length-Ratio-Matching Routing for Capacitor Arrays in Analog Integrated Circuits |
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標題: |
Optimization of Clock Gating Circuits with Timing Considerations |
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標題: |
Layout Decomposition for Trimple Pattering Lithography |
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標題: |
Analytical Placement for Modem Mixed-Size Circuit Designs |
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標題: |
Structrual-Optimization-Based Clock Network Synthesis |
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標題: |
Self-Heating-Aware Buffered Clock Tree Synthesis |
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標題: |
Analytical Placement for FPGAs |
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標題: |
Structure-Aware Placement for Datapath-Intensive Circuit Designs |
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標題: |
Double Patterning Lithography-Aware Analog Placement |
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標題: |
Lithography Optimization for Sub-22 Nanometer Technologies |
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標題: |
Routability-Driven Blockage-Aware Macro Placement |
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標題: |
Non-stitch Triple Patterning-Aware Routing Based on Conflict Graph Pre-coloring |
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標題: |
Simultaneous EUV Flare- and CMP-Aware Placement |
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標題: |
Power and Timing Optimization for Hybird SoC Designs with Asynchronous/Synchronous Designs |
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標題: |
Design Methodology for Interposer-Based 3D IC Packaging |
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標題: |
Packing and Analytical Placement for Large-Scale Heterogeneous FPGAs |
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標題: |
Metal-Only Engineering Change Order Optimization for Integrated Circuit Design |
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標題: |
Circular-Contour-Based Blockage-Aware Macro Placement |
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標題: |
Routing-Architecture-Aware Analytical Placement for Heterogeneous FPGAs |
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標題: |
Automatic Layout Synthesis for Nanometer Analog Circuit Designs |
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標題: |
A Minimum-Implant-Area-Aware Detailed Placement Algorithm with Spacing Constraints |
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標題: |
Placement Considering the Electron Beam Fogging Effect |
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標題: |
QB-Trees: Towards an Optimal Topological Representation and Its Applications to Analog Layout Designs |
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標題: |
A Redistribution Layer Routing System for Integrated Fan-Out Wafer-Level Chip-Scale Packages |
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標題: |
Blockage-Aware Terminal Propagation for Placement Wirelength Minimization |
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標題: |
Dampd-Wave Based Macro Placement for Mixed-Size Circuit Designs |
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標題: |
Integrated Spreading Based Macro Placement for Large-Scale Mixed-Size Circuit Designs |
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標題: |
Manufacturability Considering Routability and Mask-Fabrication Optimization for Next Generation Lithography |
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標題: |
Nanoscale Pattern-Based Cut Redistribution for Two-Dimensional Directed Self-Assembly |
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標題: |
Mixed-Cell-Height Detailed Placement Considering Complex Minimum-Implant-Area Constraints |
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標題: |
A Redistribution Layer Routing System for Wafer-Level Integrated Fan-Out Package-on-Packages |
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